Freescale Semiconductor MPC8313E Family Reference Manual page 1211

Port Status and Signaling Type
Port is connected and the port's
PORTSC[WKOC] bit is a one. An
over-current condition occurs.
Port is connected and the port's
PORTSC[WKOC] bit is a zero. An
over-current condition occurs.
1
Hardware interrupt issued if USBINTR[PCE] (port change interrupt enable) is set.
2
PME# asserted if enabled (Note: PME Status must always be set).
3
PME# not asserted.
16.6.12.2.1, 16-94
Periodic
Frame List
Figure 16-54. General Structure of EHCI Periodic Schedule Utilizing Interrupt Spreading
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 16-64. Behavior During Wake-Up Events (continued)
PORTSC Over-current Active (OCA), Over-current Change
(OCC) bits are set. If Port Enable/Disable bit (PE) is a one, it is
cleared. USBSTS[PCI] is set
PORTSC Over-current Active (OCA), Over-current Change
(OCC) bits are set. If Port Enable/Disable bit (PE) is a one, it is
cleared. USBSTS[PCI] is set.
Modify Figure 16-54, "General Structure of EHCI Periodic Schedule Utilizing
Interrupt Spreading," to show as follows:
•
•
•
Signaled Port Response
Linkage repeats every 8 for
remainder of frame list
Level 8 Level 4
Level 2
8
7
8
6
4
3
8
5
4
8
2
4
8
4
3
1
8
2
4
0
8
1
8
0b
8
0
Revision History
Device State
D0
[1], [2]
[1], [3]
Level 1
(Root)
2
1
• • •
1
0
2
0
not D0
[2]
[3]
A-33