Freescale Semiconductor MPC8313E Family Reference Manual page 1186

Revision History
8.5.11, 8-20
Offset 0x38
0 1 2
R
1
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4
W
Reset
16 17
R
SIRQ0
W
Reset
1
This bit is valid only if the IRQ0 signal is configured as an external maskable interrupt (SEMSR[SIRQ0] = 0)
Figure 8-14. System External Interrupt Mask Register (SEMSR)
9.3.2.1, 9-6
9.5, 9-29
9.5.2, 9-35
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
A-8
Modify Figure 8-14, "System External Interrupt Mask Register (SEMSR)," to
show as follows:
3 4 5
Change signal description of MA[14:0] from:
Assertion/Negation—The address is always driven when the memory controller is
enabled. It is valid when a transaction is driven to DRAM (when MCSn is active).
to:
Assertion/Negation—The address lines are only driven when the controller has a
command scheduled to issue on the address/CMD bus; otherwise they will be at
high-Z. It is valid when a transaction is driven to DRAM (when MCSn is active).
Change the following sentence from:
Bank sizes up to 512 Mbytes are supported, providing up to a maximum of 512
Mbytes of DDR main memory of DDR main memory.
to:
Bank sizes up to 2 Gbits (maximum total physical memory size of 4 Gbytes) are
supported, providing up to a maximum of 4 Gbits of DDR main memory per chip
select.
Add two tables for DDR1 and DDR2 Address Multiplexing for 16-Bit Data Bus
(with Interleaving Disabled) after Table 9-27, "DDR1 Address Multiplexing for
32-Bit Data Bus with Interleaving Disabled."
—
All zeros
—
All zeros
Access: Read/write
15
31
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