Freescale Semiconductor MPC8313E Family Reference Manual page 1231

Chapter 15, 15-1
15.4, 15-7
TSEC_1588_PP3 1588—Pulse out 3
Timer pulse per period 3. It is phase aligned with 1588 timer clock (chip external output pin).
15.4.1, 15-8
TSEC_1588_PP3 O
15.5.2, 15-15
15.5.3.1.3, 15-24
15.5.3.1.3, 15-24
27 FGPI Filer generated general purpose interrupt on a set of filer rule match. This bit will be set upon reception of
a frame that matches a GPI rule sequence that is specified in the filer. It is synchronized with the setting of
RXF.
0 No filer generated interrupt has occurred.
1 The filer has accepted a frame via a matching rule that the RQFCR[GPI] bit set.
15.5.3.1.4, 15-28
25–26 — Reserved
27 FGPIEN Filer general purpose interrupt enable
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Throughout the chapter remove text and references describing extraction of data
to allocate in the L2 cache. The MPC8313E does not support extraction to L2
cache.
In Table 15-1, for signal TSECn_RX_ER, in the Description column changed to:
RGMII, RTBI—Unused.
In Table 15-1, added signal TSEC_1588_PP3 as follows:
In Table 15-2, TSECn_CRS, State Meaning, changed reference from
TSECn_TX_CLK to TSECn_CRS.
In TEC_GTX-CLK125, Description column, added the following statement:
This input is not used in these modes:
• RMII
• SGMII
• MII
In Table 15-2, added Signal TSEC_1588_PP3, as follows:
1588 pulse out 3. Timer pulse per period 3. It is phase aligned with 1588 timer clock (chip external
output pin)
In Table 15-4, corrected the values for RQFCR and RQFPR as follows:
0xnnnn_nnnn
After item #3, added a fourth sub-bullet as follows:
—Special function interrupts are: FGPI, MSRO, MMRD, and MMRW
In Figure 15-4, changed bit 27 to FGPI.
In Table 15-7, add the following for bit 27, FGPI:
In Figure 15-5, bit 26, changed to FGPIEN.
In Table 15-8, changed bits 25–27 to the following:
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