Freescale Semiconductor MPC8313E Family Reference Manual page 1135

[UDMB||UDLB:0b0000] = platform clock frequency/desired baud rate. Baud rates that can be generated
by specific input clock frequencies are shown in
Figure 18-4 shows the bits in the UDMBs.
Offset: 0x0_4501, 0x0_4601
0
R
W
Reset
Figure 18-4. Divisor Most Significant Byte Registers (UDMB1 and UDMB2)
Table 18-6 describes the UDMB.
Bits Name
0–7 UDMB Divisor most significant byte
Figure 18-5 shows the bits in the UDLBs.
Offset: 0x0_4500, 0x0_4600
Reset
Figure 18-5. Divisor Least Significant Byte Registers (UDLB1 and UDLB2)
Table 18-7 describes the UDLB.
Bits Name
0–7 UDLB Divisor least significant byte. This is concatenated with UDMB.
Table 18-8 shows baud rate for a variety of input clock frequencies.
Baud Rate
(Decimal)
9,600
19,200
38,400
56,000
128,000
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 18-6. UDMB Field Descriptions
0
R
W
Table 18-7. UDLB Field Descriptions
Table 18-8. Baud Rate Examples
Divisor
Decimal
866
433
216
148
65
Table 18-8.
UDMB
All zeros
Description
UDLB
All zeros
Description
Input Clock (System
Clock) Frequency
Hex (MHz)
362 133
1B1 133
D8 133
94 133
41 133
Access: Read/write
Access: Read/write
7
Percent Error
(Decimal)
0.013
0.013
0.218
0.300
0.090
DUART
7
18-7