Freescale Semiconductor MPC8313E Family Reference Manual page 1234

Revision History
15.5.3.10.1, 15-108
6–15 TCLK_ 1588 timer reference clock period. The timer clock counter will increment by TCLK_PERIOD every time
PERIOD the accumulator register overflows. This clock period must be larger than the clock period of the timer
reference clock. For applications where user does not want the clock period to be added, they can
program this field to 1 to count the clock ticks. This field defaulted to 1 to count overflow ticks.
For nanosecond granularity on 1588 timer counter rate, the TCLK_PERIOD should be calculated using
the following equation:
15.5.3.10.9, 15-115
15.5.3.10.12, 15-117
15.5.3.10.12, 15-117
0–63 ALARM_H/L Alarm time comparator register. The corresponding alarm event in TMR_TEVENT is set when the
current time counter becomes equal to or greater than this alarm time compare value in
TMR_ALARM n _L/H. Writing the TMR_ALARM n _L register deactivates the alarm event after it has
fired. Writing the TMR_ALARM n _L followed by the TMR_ALARM n _H register rearms the alarm
function with the new compare value.
The value programmed in this register must be an integer multiple of TMR_CTRL[TCLK_PERIOD] in
order to get correct result. This register is reset to all ones to avoid false alarm after reset.
In FS mode the alarm trigger is used as an indication to the fiper start down counting. Only alarm 1
supports this mode. In FS mode, alarm polarity bit should be configured to 0 (rising edge).
15.5.3.10.16, 15-118
15.6.2.8, 15-151
15.6.2.10, 15-152
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
A-56
In Figure 15-106, bit 27, made bit 'Reserved'.
In Table 15-109, in bit 6–15 row, changed to the following:
9
TCLK_PERIOD = 10 /Nominal_Frequency
In Table 15-109, in Bit 25 row, added the following to the Description column:
'Note that this setting is reserved if CKSEL=01'.
In Bit 26 row, Description column, added the following note:
Note: Prior to initiating timer reset (setting TMSR), must gracefully stop receiver (see
MACCFG1[RX_EN] description).
In Bit row 27, deleted DBG and made bit 'Reserved'.
In Bit row 30–31, added the following:
11 RTC clock input. Note that the 1588 reference clock must be no slower than 1/7 the Rx_clk
frequency.
The default clock select is eTSEC system clock, which is always active when eTSEC is enabled.
The user must ensure the corresponding clock source is active before changing the 1588 refclk
selection to external reference, RTC, or TX clock. Selecting an inactive 1588 reference clock
may cause boundedly undefined behavior in the ethernet controller and on accesses to the
1588 registers.
In Figure 15-112, changed access from read only to read/write.
In Figure 15-115, changed access from mixed to read/write.
In Table 15-122, replaced the Description column with the following:
In Figure 15-116, changed access from mixed to read/write.
In the second paragraph, last sentence, changed to the following:
Only frames addressed specifically to the MAC's station address or a valid
multicast or broadcast address can be examined for the Magic Packet sequence.
The first three sub-bullets were changed to read:
—Receive data frame interrupts, when bits RXB or RXF in IEVENT are set
—Transmit data frame interrupts, when bits TXB or TXF in IEVENT are set
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