Freescale Semiconductor MPC8313E Family Reference Manual page 1199

15.5.3.5.5, 15-72
15.5.3.5.6, 15-73
15.5.3.6, 15-80
The transmit and receive frame counters (TR64, TR127, TR 255, TR511,
TR1K, TRMAX, and TRMGV) do not increment for aborted frames
(collision retry limit exceeded, late collision, underrurn, EBERR, TxFIFO
data error, frame truncated due to exceeding MAXFRM, or excessive
deferral)."
15.5.3.6.17, 15-87
15.5.3.6.41, 15-99
15.5.3.6.44, 15-101
15.5.3.6.45, 15-102
15.5.3.9.2, 15-110
15.5.3.10, 15-110
15.5.3.10.1, 15-111
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
In Table 15-44, "MAXFRM Descriptions," add maximum value limit to
MAXFRM[Maximum Frame] field description by modifying the first sentence to
read as follows
"This field is set to 0x0600 (1536 bytes) by default and always must be set to a
value greater than or equal to 0x0040 (64 bytes), but not greater than 0x2580
(9600 bytes)."
In Table 15-45, "MIIMCFG Field Descriptions," remove references to CCB
clock.
Add the following note to the end of this section, following an existing note, and
prior to Section 15.5.3.6.1, "Transmit and Receive 64-Byte Frame Counter
(TR64)":
In Table 15-72, "RFLR Field Descriptions," add the following content to the
RFLR[RFLR] (bits 16–31) field description:
"Frames tagged with a single VLAN tag are checked for valid length based on
bytes 17–18 (rather than 13–14). Frames tagged (stacked) with multiple VLAN
tags are not checked for valid length."
In Table 15-96, "TOVR Field Descriptions," correct TOVR[TOVR] (bits 20–31)
field description to read as follows:
"Transmit oversize frame counter. Increments each time a frame is transmitted
which exceeds 1518 (non VLAN) or 11522 (VLAN) with a correct FCS value."
In Figure 15-95, "Carry Register 1 (CAR1) Register Definition," change the
access designation for CAR1 registers to be "w1c."
In Figure 15-96, "Carry Register 2 (CAR2) Register Definition," change the
access designation for CAR2 registers to be "w1c."
In Figure 15-104, "RFBPTR0–RFBPTR7 Register Definition," change register
offset designation to read as follows:
"Offset
eTSEC1:0x2_4C44+8×n; eTSEC2:0x2_5C44+8×n
Change title of section from "Hardware Assist for IEEE 1588 Complaint
Timestamping" to "IEEE 1588-Compatible Timestamping Registers"
In Figure 15-105, "TMR_CTRL Register Definition," make bits 20 and 21 of
TMR_CTRL to be reserved.
NOTE
Revision History
A-21