Freescale Semiconductor MPC8313E Family Reference Manual page 1220

Revision History
5.3.2.4, 5-18
Offset 0x00110
0
R
BUFGTX
BUFMDIO —
125
W
Reset
16 17
R
TSEC1588
W
Reset
5.3.2.4, 5-19
5.3.2.4, 5-19
0 BUFGTX125 0 A signal is supplied from an external PHY or oscillator to TSEC1_GTX_CLK125 has the same
1 A 2.5-V signal is supplied to TSEC1_GTX_CLK125 from an external PHY or oscillator, and the LVdbb
1 BUFMDIO 0 A 3.3-V signal is supplied from external PHY to TSEC1_MDIO
1 A 2.5-V signal is supplied from external PHY to TSEC1_MDIO
2 — Reserved. Should be cleared.
5.3.2.4, 5-20
12–15 — Reserved. Should be cleared.
16–17 TSEC1588 00 Selects 1588 pins muxed with eTSEC1 (default)
01 Selects 1588 pins muxed with LA[10:15] pads.
10 Selects 1588 pins muxed with UART2 + I2C1 pads.
11 Reserved
5.3.2.5, 5-21
5.3.2.6, 5-23
5.3.2.6, 5-24
5.3.2.7.1, 5-26
5.3.2.8, 5-27
Note:
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
A-42
In Figure 5-13, replace with the following:
2 3 4
PCIHPE
18 19 20
TSECDP TSECBDP
In Figure 5-13, "
System Priority Configuration Register (SPCR),"
updated to reflect dependency on CFG_RESET_SRC
In Table 5-26, changed bits 0 thru 2 to the following:
voltage level as the LVddb power supply. (Default)
power supply has a 3.3-V voltage level.
In Table 5-26, changed bits 12 thru 17 to the following:
In Figure 5-14, added bit numbers for bit 17, 18, 25, and 26 to the figure.
In Table 5-28, bit 7, changed the reset value to 1.
In Table 5-29, updated SICRH[7] and corresponding footer.
In Table 5-30, corrected bits 30 and 31 from LVDD1 and LVDD2 to lvddb and
lvdda, respectively.
Rewrote the first paragraph as follows:
The DDR debug configuration enables a DDR memory controller to enter debug
mode in which the DDR SDRAM source ID field and data valid strobe are driven
onto one of two optional sets of pins:
In Table 5-30, added the following note in the Description column for DDR_cfg:
DDR_cfg must be set according to the logical type of the DDR memory devices, as it effects logic
behavior of the DDR controller as well as the physical parameters of the DDR I/O pads.
5 6 7 8
— PCIPR OPT
All zeros
21 22 23 24
TSECEP
All zeros
9 10 11 12
TBEN COREPR
25 26 27 28
—
reset value
Freescale Semiconductor
Access:
Read/Write
15
—
29 30 31