Freescale Semiconductor MPC8313E Family Reference Manual page 1037

and queue head data structure. The S and C
start-splits and complete splits (respectively).
Periodic Schedule
7
Micro-Frame
Case 1:
Normal Case
Case 2a:
End of Frame
Case 2b:
End of Frame
Case 2c:
End of Frame
HS/FS/LS Bus
6
Micro-Frame
B-Frame N–1
Figure 16-53. Split Transaction, Interrupt Scheduling Boundary Conditions
The scheduling cases are:
• Case 1: The normal scheduling case is where the entire split transaction is completely bounded by
a frame (H-Frame in this case).
• Case 2a through Case 2c: The USB 2.0 hub pipeline rules states clearly, when and how many
complete-splits must be scheduled to account for earliest to latest execution on the full/low-speed
link. The complete-splits may span the H-Frame boundary when the start-split is in microframe 4
or later. When this occurs, the H-Frame to B-Frame alignment requires that the queue head be
reachable from consecutive periodic frame list locations. System software cannot build an efficient
schedule that satisfies this requirement unless it uses FSTNs.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
labels indicate microframes where software can schedule
n
0 1 2 3
S C0 C1
7 0 1 2
H-Frame N
4 5 6 7
C2
S
S C0
S C0 C1
3 4 5 6
B-Frame N
Universal Serial Bus Interface
0 1
C0 C1
C1 C2
C2
7 0
B-Frame N+1
16-95