Freescale Semiconductor MPC8313E Family Reference Manual page 1215

16.8.3.3.1, 16-135
16.8.4, 16-142
ENDPOINTLISTADDR
Up to
6 Elements
16.8.5.3, 16-145
16.9.5.1, 16-153
16.10, 16-156
PHY_CLK
DATA
DIR
STP
NXT
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Modify the second sentence in the second paragraph to say as follows:
"This FIFO is split into virtual channels so that the leading data can be stored for
any endpoint."
Modify Figure 16-64, "Endpoint Queue Head Diagram," to show as follows:
Endpoint Queue Heads
Endpoint QH 0—Out
Endpoint QH 0—In
Endpoint QH 1—Out
•
•
•
Figure 16-64. Endpoint Queue Head Diagram
Modify the list item #7 and list item #8 of Case 2: Link list is not empty as follows:
7. If status bit read in (4) is '1' DONE.
8. If status bit read in (4) is '0' then Goto Case 1: Step 1.
Modify the last sentence as follows:
"That is, 60-MHz transceiver clock for 8-bit physical interfaces and full-speed
serial interfaces or 30-MHz transceiver clock."
Modify Figure 16-72, "ULPI Register Read" to show as follows:
TX CMD(RegRd)
Figure 16-72. ULPI Register Read
Transfer Buffer Pointer
Transfer Buffer Pointer
Transfer
Buffer
Pointer
Endpoint Transfer Descriptor
DATA
Revision History
Transfer
Buffer
Transfer
Buffer
Transfer Buffer Pointer
Transfer Transfer
Buffer Buffer
A-37