Freescale Semiconductor MPC8313E Family Reference Manual page 1224

Revision History
10.3.1.16, 10-33
10.4.2, 10-45
eLBC in GPCM
10.4.2.1, 10-46
Option Register Attributes
TRLX EHTR
0 0
0 0
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
0 1
0 1
1 0
1 0
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
A-46
In Table 10-22, for bits 27-31, changed the first paragraph to the following:
System clock divider. Sets the frequency ratio between the system clock and the
local bus clock. The system clock is equivalent to csb_clk or twice csb_clk (if
RCWL[LBCM] is set). Only the values shown below are allowed.
In Table 10-23, bits 16–19, changed the first sentence to read: '... high (CW0,
CW1, RBW and RSW), FCM ...'.
Replaced Figure 10-31 with the following:
LCS n
LOE
LWE0
Mode
LA[6:25]
LAD[0:7]
Replaced Table 10-30 with the following:
XACS ACS t
ARCS
0 0X 0
0 10 ¼
(½)
0 11 ½
1 0X 0
1 10 1
1 11 2
0 0X 0
0 10 ¼
(½)
0 11 ½
1 0X 0
1 10 1
1 11 2
0 0X 0
0 10 1¼
(1½)
CE
OE
WE
Memory/Peripheral
A[19:0]
Data[7:0]
Signal Timing (LCLK Clock Cycles)
t t
CSRP AOE
2+SCY 1
1¾+SCY 1
(2+SCY)
1½+SCY 1
2+SCY 1
1+SCY 1
1+SCY 2
2+SCY 1
1¾+SCY 1
(1½+SCY)
1½+SCY 1
2+SCY 1
1+SCY 1
1+SCY 2
2+2×SCY 1
1¾+2×SCY 2
(1½+2×SCY)
1
t t
OEN RC
0 2+SCY
0 2+SCY
0 2+SCY
0 2+SCY
0 2+SCY
0 3+SCY
1 3+SCY
1 3+SCY
1 3+SCY
1 3+SCY
1 3+SCY
1 4+SCY
4 6+2×SCY
4 7+2×SCY
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