Freescale Semiconductor MPC8313E Family Reference Manual page 1239

Table 15-160. Tx Frame Control Block Description (continued)
Bytes Bits Name
4–5 0–15 PHCS
6–7 0–15 VLCTL/
PTP_ID
15.6.7.3, 15-182
15.7.1.6, 15-203
Signals
TX n /TX n
RX n /RX n
SGMII mode initialization sequence is very similar to TBI mode initialization. Additional initialization is
required for the SerDes. An example of SGMII mode initialization sequence is shown in Table 15-176.
SGMII mode utilizes the internal TBI PHY. The internal TBI PHY only
auto-negotiates at 1 Gbps. However, 10 Mbps and 100 Mbps speeds are
supported in SGMII mode. It is recommended that the external PHY inform
the MAC if the desired link speed is not 1 Gbps. Software can perform MII
management cycles to determine the external PHY link speed and program
ECNTRL and MACCFG2 accordingly.
15.7.1.6, 15-203
15.7.1.6, 15-204
Writing to MII Mgmt Control with 16-bit data intended for TBI's AN Advertisement register,
This advertises to the Link Partner that the TBI supports PAUSE and Full Duplex mode and does not support Half Duplex mode.
16.3, 16-5
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Pseudo-header checksum (16-bit one's complement sum with carry wraparound, but without
result inversion) for TCP or UDP packets, calculated by software. Valid only if NPH = 1.
VLAN control word for insertion in the transmitted VLAN tag. Valid only if VLN = 1.Tx PTP
packet identification number. This number will be copied into the Tx PTP packet time stamp
identification field. PTP field takes precedence over VLN field.
In Table 15-163, offset 4–7, bits 0–31, in the Description column, added the
following sentence: 'For best performance, use 64-byte aligned receive buffer
pointer addresses'.
Replaced the first paragraph with the following:
Table 15-177. SGMII Interface Signal Configuration (4-Wire)
SerDes Signals
Frequency [MHz] 1250
Voltage [V] LVDS
No. of
I/O
Signals
O
I
Sum
In Table 15-179, removed references to TBICON[Enable Wrap] and
TBICON[Comma Detect].
In Table 15-179, changed the following row to read:
Perform an MII Mgmt write cycle to TBI.
MIIMCON[0000_0000_0000_0000_0000_0001_1010_0000]
In Table 16-3, Section/Page column, corrected page numbers.
Description
SGMII Interface
Frequency [MHz] 1250
Voltage [V] LVDS
Signals
2 TXD
2 RXD
4 Sum
NOTE
Revision History
No. of
I/O
Signals
O 2
I 2
4
A-61