Freescale Semiconductor MPC8313E Family Reference Manual page 1165

SPIM bit enables and clearing a SPIM bit masks the corresponding interrupt. Unmasked SPIE bits must
be cleared before the core clears its internal interrupt requests.
Offset 0x028
0
R
W
Reset
Table 19-6 describes the SPIM fields.
Bits Name
0–16 — Reserved
17 LT Last character transmitted
0 LT event will not cause an SPI interrupt
1 LT event causes an SPI interrupt
18 DNR In slave mode data not ready
0 Slave DNR event will not cause an SPI interrupt
Note: 1Slave DNR event causes an SPI interrupt
19 OV Slave/Master Overrun interrupt mask
0 Slave/Master Overrun event will not cause an SPI interrupt
1 Slave/Master Overrun event causes an SPI interrupt
20 UN Slave Underrun interrupt mask
0 Slave Underrun event will not cause an SPI interrupt
1 Slave Underrun event causes an SPI interrupt
21 MME Multimaster error interrupt mask
0 Multimaster error event will not cause an SPI interrupt
1 Multimaster error event causes an SPI interrupt
22 NE Not Empty interrupt mask
0 Not Empty event will not cause an SPI interrupt
1 Not Empty event causes an SPI interrupt
23 NF Not Full interrupt mask
0 Not Full event will not cause an SPI interrupt
1 Not Full event causes an SPI interrupt
24–31 — Reserved
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
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Figure 19-8. SPIM—SPI Mask Register Definition
Table 19-6. SPIM Field Descriptions
16 17 18 19 20 21
LT DNR OV UN MME NE NF
All zeros
Description
Serial Peripheral Interface
Access: Read/write
22 23 24
—
31
19-13