Freescale Semiconductor MPC8313E Family Reference Manual page 1244

Revision History
A.3 Changes From Revision 0 to Revision 1
Major changes to the MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual,
from Revision 0 to Revision 1 are as follows:
Section, Page
1.1, 1-4
1.1, 1-6
1.2.6, 1-14
2.3, 2-5
3.1, 3-1
3.1, 3-20
4.3.1.1, 4-10
4.3.1.3, 4-11
4.3.2, 14-13
4.3.3.3.2, 4-27
4.4.3, 4-31
4.4.5, 4-33
4.4.7, 4-34
4.5.2.3, 4-42
4.5.2.3, 4-41
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
A-66
Throughout book, removed 'MPC8313E and MPC8313 specific,' text. Removed
LSYNC_OUT and LSYNC_IN.
Throughout book—removed internal signal LBC_PM_REF_10 references.
Throughout book—fixed the direction of signals in figures and tables.
Throughout chapter, replaced 'On-chip USB-2.0 full-speed/high-speed PHY with
ULPI (UTMI + low-pin interface),' with the following:
On-chip USB-2.0 full-speed/high-speed PHY with UTMI
Replaced 'Supports wake-up from Ethernet Magic Packet, USB, GPIO, and PCI
(PME input as host),' with the following:
Supports wake-up from Ethernet Magic Packet, USB, GPIO, PCI (PME input as
host), timer, and external interrupts
Removed Section 1.2.6, "Serial ATA (SATA) Controller."
In Table 2-2, changed the reset value of SWSRR from 0x0000_0000 to 0x0000,
as it is a 16-bit register.
Throughout book—added signals: USB_PHY_PWR, USB_PHY_GND,
USB_VDDA, USB_VSSA, USB_PLL_PWR1, USB_PLL_PWR3,
USB_PLL_GND0, USB_PLL_GND1, USB_VSSA_BIAS, and
USB_VDDA_BIAS.
Removed signals: SD_PLL_TPA_ANA and SD_PLL_TPD.
Removed Table 3-3, because of inconsistencies between MPC8313 hardware
specification document and the reference manual.
In Table 4-5, for offset 0100, changed PCI frequency range from 25–66.666 MHz
to 24–66.666 MHz.
In Table 4-6, modified the description for CFG_CLKIN_DIV.
In Table 4-8, added more description to DDRCM bit.
Table 4-25, for bits 1, 3, 12–15, and 20–27, removed 'Reserved, should be
cleared,' and added 'Reserved.' Also reformatted the table.
Removed overbars for the signal CFG_CLKIN_DIV.
Modified Ethernet clocking description.
Deleted Figure 4-8 and replaced it with Table 4-8, "System Clock Frequencies."
Table 4-37, changed the description for [4:5], [12:14], and [16:31] by removing
'should be cleared.'
Table 4-38, in ENCCM description, replaced 'Encryption core clock mode,' with
'Encryption core and I2C1 clock mode.'
Changes
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