Freescale Semiconductor MPC8313E Family Reference Manual page 1207

Signal
USBDR_DRIVE_VBUS
USBDR_PWRFAULT
USBDR_PCTL0
USBDR_PCTL1
16.3, 16-6
Offset
0x14C FRINDEX—USB frame index
0x154 PERIODICLISTBASE—Frame list base address
0x1A4 OTGSC—On-The-Go status and control
0x1AC ENDPTSETUPSTAT—Endpoint setup status
1
This register has separate functions for the host and device operation; the host function is listed first in the table.
16.3.2.4, 16-18
16.3.2.6, 16-20
16.3.2.14, 16-26
16.3.2.14, 16-28
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
I/O
I/O This pin is used to enable/disable power (VBus) on applications supporting port power
switching. This signal is not applicable to device only applications.
State Asserted—Vbus power enabled.
Meaning Negated—Vbus power disabled.
I Power fault. USBDR_PWRFAULT indicates whether a power fault occurred on the USB port
Vbus.
State Asserted—Indicates that a Vbus fault occurred. Applications that support power
Meaning switching must shut down Vbus power.
Negated—Indicates normal operation.
Timing Synchronous to PHY_CLK.
O Port control 0. USBDR_PCTL0 controls the port status indicator LED 0 when in host mode.
State Asserted—LED on.
Meaning Negated—LED off.
Timing Synchronous to PHY_CLK.
O Port control 1. USBDR_PCTL1 controls the port status indicator LED 1 when in host mode.
State Asserted—LED on.
Meaning Negated—LED off.
Timing Synchronous to PHY_CLK.
In Table 16-3, "USB Interface Memory Map," modify the rows of the following
registers. Note that only affected registers are shown.
Register
In Figure 16-11, "USB Frame Index (FRINDEX)," change the reset values from
"0x0000_nnnn" to "All zeros."
In Figure 16-12, "Periodic Frame List Base Address (PERIODICLISTBASE),"
modify the reset value from "0xnnnn_0000" to "All zeros"
In Figure 16-20, "Port Status and Control (PORTSC)," change bit 20 to WKCN
from WLCN.
In Table 16-23, "PORTSC Register Field Descriptions," change WLCN (bit 20)
to WKCN.
Description
Access
R/W All zeros
1
R/W All zeros
Mixed 0x0000_1030
w1c 0x0000_0000
Revision History
Reset Section/Page
16.3.2.4/16-18
16.3.2.6/16-19
16.3.2.15/16-31
16.3.2.17/15-35
A-29