Freescale Semiconductor MPC8313E Family Reference Manual page 1222

Revision History
9.5.5.1, 9-34
2 Gbits
9.6.1, 9-50
Chapter 10
10.1.3, 10-3
10.2, 10-4
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
A-44
In Table 9-7, Bits 13–15 row, changed 011–111 Reserved to 011 Reserved.
In Table 9-26, added the following row:
256Mbits x 8
Changed 'Row x Column x Sub-Bank Bits' column for the 1 Gbits, 2 Gbits, and
4 Gbits rows to: ... x 2.
In Table 9-35, for ODT_PD_EXIT, changed it to be set to 0001 for DDR1; for
FOUR_ACT, changed it to be set for 00001 for DDR1.
Reformatted registers throughout Chapter 10, "Enhanced Local Bus Controller."
Modified frequencies 333 and 666 MHz to 33.3 and 66.6 MHz, respectively.
Added eLBC IP Rev. 1.1 features.
Removed references to PLL.
In the first paragraph, second sentence replace with the following:
The internal transaction address is limited to 32 bits, so all chip selects must fall
within the 4-Gbyte window addressed by the internal transaction address. When a
memory transaction is dispatched to the eLBC, the internal transaction address is
compared with the address information of each bank (chip select).
In the first paragraph, last sentence, replaced with the following:
Thus, with the eLBC in GPCM or FCM, or UPM mode, only one of the four chip
selects is active at any time for the duration of the transaction except in the case
of UPM refresh where all UPM machines that are enabled for refresh have
concurrent chip select assertion.
In Table 10-2, LGPL0/LFCLE row, changed the first sentence in the State
Meaning to read:
Asserted/Negated—In UPM mode, LGPL0 is one of six general purpose signals;
it is driven with a value programmed into the UPM array.
In the LGPL1/LFALE row, changed the first sentence in the State Meaning to
read:
Asserted/Negated—In UPM mode, LGPL1 is one of six general purpose signals;
it is driven with a value programmed into the UPM array.
In the LOE/LGPL2/LFRE row, changed the second and third sentences in the
State Meaning to read:
In UPM mode, LGPL2 is one of six general purpose signals; it is driven with a
value programmed into the UPM array.
LFRE enables data read cycles from NAND Flash EEPROMs controlled by FCM.
In the LGPL3/LFWP row, changed the first sentence in the State Meaning to read:
Asserted/Negated—In UPM mode, LGPL3 is one of six general purpose signals;
it is driven with a value programmed into the UPM array.
15 x 10 x 2 1 Gbytes 2 Gbytes
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