Freescale Semiconductor MPC8313E Family Reference Manual page 1184

Revision History
5.7.6.1, 5-62
5.7.6.1, 5-62
5.7.6.3, 5-63
6.2, 6-2
0x08 Arbiter Event Enable Register (AEER)
6.2.3, 6-5
6.2.3 Arbiter Event Enable Register (AEER)
Arbiter event enable register (AEER) specifies, which kind of events are considered as error events. If
event is defined as non-error event, it also won't be reported neither in event register nor in event attributes
and address registers. For transfer types, that are not defined as error events, arbiter also does not end
address/data tenures. Figure 6-3
Offset 0x08
0
R
W
Reset
Table 6-4 defines the bit fields of AEER.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
A-6
In addition, replace Timing description with the following:
"Assertion/Negation—TOUTn changes occur on the rising edge of the timer input
clock."
In the second paragraph following the bulleted list, change 65,537 to 65,536.
Change the sentence in the third paragraph from:
"The best resolution of the timer is one clock cycle (3 ns at a 333-MHz system
clock, for example). The maximum period (when the reference value is all ones
and the prescaler divides by 256) for one 16-bit timer is ~50 ms at 333 MHz."
to:
"The best resolution of the timer is one clock cycle (5.9 ns at 167 MHz system
clock, for example). The maximum period (when the reference value is all ones
and the prescaler divides by 256) for one 16-bit timer is ~405 s at 167 MHz."
In the Note, replace "the counter begins counting after..." to "the counter begins
or stops counting after..."
Add row for Arbiter Event Enable Register in Table 6-1, "Arbiter Register Map,"
as follows:
Add a new section on Arbiter Event Enable Register, which was missing. This
section will appear before Section 6.2.3. The subsequent sections, figures, and
tables are re-numbered.
shows the fields of AEER.
—
Figure 6-3 Arbiter Event Enable Register (AEER)
R/W
25
All zeros
0x0000_007F 6.2.3/6-5
Access: Read/Write
26 27 28 29 30
ETEA RES ECW AO DTO ATO
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