Freescale Semiconductor MPC8313E Family Reference Manual page 1228

Revision History
ms
b
0 1 2 3
AMX = 10
MxMR[AM] = 011
(Row)
AMX = 00
(Col)
AMX = 10
MxMR[AM] = 100
(Row)
AMX = 00
(Col)
AMX = 10
MxMR[AM] = 101
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
(Row)
AMX = 00
(Col)
AMX = 10
MxMR[AM] = 110
AMX = 10
MxMR[AM] = 111
10.4.4.4.7, 10-84
AMX must not change values in any RAM word which begins a loop.
10.4.4.5, 10-86
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
A-50
Table 16-65. UPM Address Multiplexing (continued)
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
LAD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
LAD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
LAD
Added the following note at the end of the section:
Replaced second paragraph with the following:
However, programming WAEN = 1 and UTA = 1 in the same RAM word, under
certain conditions, allows the UPM to treat LUPWAIT as a synchronous signal,
which must meet set-up and hold times in relation to the rising edge of the bus
clock. The conditions are as follows:
•The PLL must be enabled, that is, LCRR[PBYP] = 0.
•DLT3 bit must be cleared in the same RAM word to avoid mid-sampling of read
data.
•LBCR[LPBSE] = 0 and MXMR[GPL4] = 1
•The combination WAEN = 1 and UTA = 1 should be in the RAM word next to
the word which gets frozen by LUPWAIT assertion. This condition limits the
use of this mode to cases where the exact cycle of LUPWAIT assertion is
predictable.
In this mode, as soon as UPM samples LUPWAIT negated on the rising edge of
the bus clock, it immediately generates an internal transfer acknowledge, which
allows a data transfer one bus clock cycle later. The generation of transfer
acknowledge is early because LUPWAIT is not re-synchronized. The
acknowledge occurs early or normally depending on whether the UPM was
already frozen in WAIT cycles or not. This feature allows the synchronous
negation of LUPWAIT to affect a data transfer, even if UTA, WAEN, and LAST
are set simultaneously.
Internal Transaction Address
LA
LA
14
LA
LAD
13 14
Reserved
Reserved
NOTE
21 22 23 24 25 26 27 28 29 30 31
LAD LA
15 16 17 18 19 20 21 22 23 24 25
LAD LA
15 16 17 18 19 20 21 22 23 24 25
LA
15 16 17 18 19 20 21 22 23 24 25
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