Freescale Semiconductor MPC8313E Family Reference Manual page 1195

15.4, 15-7
15.4, 15-8
Signal Name
SD_REF_CLK, SerDes PLL reference clock (and complement)
SD_REF_CLK
TXA/TXA, SGMII transmit data (and complement)
TXB/TXB
RXA/RXA, SGMII receive data (and complement)
RXB/RXB
15.4.1, 15-11
Signal I/O
SD_REF_CLK,
SD_REF_CLK
TXA/TXA, O
TXB/TXB
RXA/RXA,
RXB/RXB
15.5.1, 15-11
15.5.2, 15-19
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
In Table 15-1, "eTSECn Network Interface Signal Properties," change statement
in the signal description for TSECn_TXD[3:0]:
from:
"RMII—TXD[3:2] unused; output driven zero"
to:
"RMII—TXD[3:2] unused"
In Table 15-1, "eTSECn Network Interface Signal Properties," add signals
TXB/TXB, RXB/RXB (previously missing)
In Table 15-2, "eTSEC Signals—Detailed Signal Descriptions," add 3 rows to
table for SD_REF_CLK/SD_REF_CLK; TXA/TXA, TXB/TXB; RXA/RXA,
RXB/RXB—with detailed description of their relation to eTSEC1 and eTSEC2
(after TSEC_1588_ALARM2 signal):
I SerDes PLL reference clock (and complement)
SGMII transmit data (and complement)
When in SGMII interface mode:
• eTSEC1 utilizes TXA/TXA
• eTSEC2 utilizes TXB/TXB
I SGMII receive data (and complement)
When in SGMII interface mode:
• eTSEC1 utilizes RXA/RXA
• eTSEC2 utilizes RXB/RXB
In Table 15-3, "Module Memory Map Summary," make bits A00–AFF reserved
as FIFO mode is not supported.
In Table 15-4, "Module Memory Map," change the access designation for CAR1
and CAR2 registers to be "w1c."
Function
Description
Revision History
Reset
State
—
—
—
A-17