Riicnsr1 - I²C Bus Status Register 1 - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.3.9 RIICnSR1 — I²C Bus Status Register 1
Access: RIICnSR1 is a 32-bit readable/writable register.
RIICnSR1L and RIICnSR1H are 16-bit readable/writable registers.
RIICnSR1LL, RIICnSR1LH, RIICnSR1HL, and RIICnSR1HH are 8/1-bit readable/writable registers.
Address: RIICnSR1: <RIICn_base> + 0020
RIICnSR1L: <RIICn_base> + 0020
RIICnSR1LL: <RIICn_base> + 0020
RIICnSR1HH: <RIICn_base> + 0023
Initial Value: 0000 0000
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Note 1. Only 0 can be written to this bit.
Table 18.14
Bit Position
31 to 8
7
6
5
4
3
2
1
0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
, RIICnSR1H: <RIICn_base> + 0022
H
, RIICnSR1LH: <RIICn_base> + 0021
H
H
This register is initialized by any reset.
H
28 27 26
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R
RIICnSR1 register contents
Bit Name Function
― Reserved
These bits are read as 0. The write value should be 0.
HOA Host Address Detection Flag
0: Host address is not detected.
1: Host address is detected.
— Reserved
This bit is read as 0. The write value should be 0.
DID Device-ID Address Detection Flag
0: Device-ID command is not detected.
1: Device-ID command is detected.
— Reserved
This bit is read as 0. The write value should be 0.
GCA General Call Address Detection Flag
0: General call address is not detected.
1: General call address is detected.
AAS2 Slave Address 2 Detection Flag
0: Slave address 2 is not detected.
1: Slave address 2 is detected.
AAS1 Slave Address 1 Detection Flag
0: Slave address 1 is not detected.
1: Slave address 1 is detected.
AAS0 Slave Address 0 Detection Flag
0: Slave address 0 is not detected.
1: Slave address 0 is detected.
H
, RIICnSR1HL: <RIICn_base> + 0022
H
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— — HOA —
0 0 0 0
R R R(/W) R
*1
18. I²C Bus Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
DID — GCA AAS2
0 0 0 0
R(/W) R R/W R(W)
*1 *1 *1
,
H
17 16
— —
0 0
R R
1 0
AAS1 AAS0
0 0
R(/W) R(/W)
*1 *1
18-27