I 2 C Bus Status Register (Icsr) - Renesas H8S/2633 Series Hardware Manual

Bit 0—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop
conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit
start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP.
This bit is always read as 1. If 1 is written, the data is not stored.
Bit 0
SCP Description
0 Writing 0 issues a start or stop condition, in combination with the BBSY flag
1 Reading always returns a value of 1
Writing is ignored
2
18.2.6 I C Bus Status Register (ICSR)
Bit : 7
ESTP
Initial value : 0
R/W : R/(W)*
Note: * Only 0 can be written, for flag clearing.
ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge
confirmation and control.
ICSR is initialized to H'00 by a reset and in hardware standby mode.
6 5
STOP IRTR AASX
0 0
R/(W)* R/(W)* R/(W)*
4 3 2
AL AAS
0 0 0
R/(W)* R/(W)*
(Initial value)
1 0
ADZ ACKB
0
0
R/(W)* R/W
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