C Bus Status Register (Icsr) - Renesas HD6417641 Hardware Manual

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Section 16 I C Bus Interface 2 (IIC2)
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16.3.5 I

C Bus Status Register (ICSR)

ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status.
ICSR is initialized to H'00 by a power-on reset.
Bit Bit Name
7 TDRE
6 TEND
5 RDRF
Rev. 4.00 Sep. 14, 2005 Page 484 of 982
REJ09B0023-0400
Initial
Value R/W Description
0 R/W Transmit Data Register Empty
[Setting conditions]
•
•
•
•
[Clearing conditions]
•
•
0 R/W Transmit End
[Setting conditions]
•
•
[Clearing conditions]
•
•
0 R/W Receive Data Register Full
[Setting condition]
•
[Clearing conditions]
•
•
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
When TRS is set
When the start condition (including retransmission)
is issued
When slave mode is changed from receive mode to
transmit mode
When 0 is written in TDRE after reading TDRE = 1
When data is written to ICDRT
When the ninth clock of SCL rises with the I
format while the TDRE flag is 1
When the final bit of transmit frame is sent with the
clock synchronous serial format
When 0 is written in TEND after reading TEND = 1
When data is written to ICDRT with an instruction
When a receive data is transferred from ICDRS to
ICDRR
When 0 is written in RDRF after reading RDRF = 1
When ICDRR is read with an instruction
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C bus