C Bus Status Register (Icsr) - Renesas H8S/2100 Series Hardware Manual

2
Section 17 I C Bus Interface (IIC)
2
17.3.6 I

C Bus Status Register (ICSR)

ICSR consists of status flags. Also see tables 17.5 and 17.6.
Bit Bit Name
7 ESTP
6 STOP
5 IRTR
Rev. 1.00 May 09, 2008 Page 512 of 954
REJ09B0462-0100
Initial
Value R/W Description
0 R/(W)* Error Stop Condition Detection Flag
This bit is valid in I
[Setting condition]
•
[Clearing conditions]
•
•
0 R/(W)* Normal Stop Condition Detection Flag
This bit is valid in I
[Setting condition]
•
[Clearing conditions]
•
•
2
0 R/(W)* I
Request Flag
Indicates that the I
interrupt request to the CPU, and the source is
completion of reception/transmission of one frame.
When the IRTR flag is set to 1, the IRIC flag is also set
to 1 at the same time.
[Setting conditions]
•
When the ICDRE or ICDRF flag in ICDR is set to 1
when AASX = 1
•
When the ICDRE or ICDRF flag is set to 1
[Clearing conditions]
•
•
2
C bus format slave mode.
When a stop condition is detected during frame
transfer.
When 0 is written in ESTP after reading ESTP = 1
When the IRIC flag in ICCR is cleared to 0
2
C bus format slave mode.
When a stop condition is detected after frame
transfer completion.
When 0 is written in STOP after reading STOP = 1
When the IRIC flag is cleared to 0
C Bus Interface Continuous Transfer Interrupt
2
C bus interface has issued an
2
I C bus format slave mode:
Master mode or clocked synchronous serial format
2
mode with I C bus format:
When 0 is written after reading IRTR = 1
When the IRIC flag is cleared to 0 while ICE is 1