C Bus Status Register (Icsr) - Renesas H8S/2111B Hardware Manual

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13.3.6 I

C Bus Status Register (ICSR)

ICSR consists of status flags. Also see tables 13.4 and 13.5.
Bit Bit Name
7 ESTP
6 STOP
5 IRTR
Initial
Value R/W
0 R/(W)*
0 R/(W)*
0 R/(W)*
Description
Error Stop Condition Detection Flag
2
This bit is valid in I C bus format slave mode.
[Setting condition]
When a stop condition is detected during frame
transfer.
[Clearing conditions]
•
When 0 is written in ESTP after reading ESTP = 1
•
When the IRIC flag in ICCR is cleared to 0
Normal Stop Condition Detection Flag
2
This bit is valid in I C bus format slave mode.
[Setting condition]
When a stop condition is detected after frame transfer
completion.
[Clearing conditions]
•
When 0 is written in STOP after reading STOP = 1
•
When the IRIC flag is cleared to 0
2
I C Bus Interface Continuous Transfer Interrupt
Request Flag
2
Indicates that the I C bus interface has issued an
interrupt request to the CPU, and the source is
completion of reception/transmission of one frame in
continuous transmission/reception. When the IRTR flag
is set to 1, the IRIC flag is also set to 1 at the same
time.
[Setting conditions]
2
I C bus format slave mode:
•
When the ICDRE or ICDRF flag in ICDR is set to 1
when AASX = 1
Master mode or clocked synchronous serial format
2
mode with I C bus format:
•
When the ICDRE or ICDRF flag is set to 1
[Clearing conditions]
•
When 0 is written after reading IRTR = 1
•
When the IRIC flag is cleared to 0 while ICE is 1
Rev. 1.00, 05/04, page 297 of 544