C Bus Status Register (Icsr) - Renesas H8S/2437 Hardware Manual

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17.3.5 I

C Bus Status Register (ICSR)

ICSR confirms interrupt request flags and status.
Bit Bit Name Initial Value R/W
7 TDRE 0
6 TEND 0
5 RDRF 0
4 NACKF 0
Description
R/W Transmit Data Empty
[Setting condition]
•
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE = 1
•
When data is written to ICDRT
R/W Transmit end
[Setting condition]
•
When the ninth clock of SCL rises while the TDRE flag
is 1
[Clearing conditions]
•
When 0 is written to TEND after reading TEND = 1
•
When data is written to ICDRT
R/W Receive Data Full
[Setting condition]
•
When receive data is transferred from ICDRS to ICDRR
[Clearing conditions]
•
When 0 is written to RDRF after reading RDRF = 1
•
When data is read from ICDRR
R/W No Acknowledge Detection Flag
[Setting condition]
•
When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER is 1
[Clearing condition]
•
When 0 is written to NACKF after reading NACKF = 1
Rev. 1.00, 09/03, page 485 of 704