C Bus Status Register (Icsr) - Renesas H8 Series Hardware Manual

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15.3.5 I

C Bus Status Register (ICSR)

ICSR performs confirmation of interrupt request flags and status.
Bit Bit Name
7 TDRE
6 TEND
5 RDRF
Initial
Value R/W Description
0 R/W Transmit Data Register Empty
[Setting conditions]
•
•
•
•
[Clearing conditions]
•
•
0 R/W Transmit End
[Setting conditions]
•
•
[Clearing conditions]
•
•
0 R/W Receive Data Register Full
[Setting condition]
•
[Clearing conditions]
•
•
Section 15 I
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
When TRS is set
When a start condition (including re-transfer) has
been issued
When transmit mode is entered from receive mode in
slave mode
When 0 is written in TDRE after reading TDRE = 1
When data is written to ICDRT with an instruction
When the ninth clock of SCL rises with the I
format while the TDRE flag is 1
When the final bit of transmit frame is sent with the
clock synchronous serial format
When 0 is written in TEND after reading TEND = 1
When data is written to ICDRT with an instruction
When a receive data is transferred from ICDRS to
ICDRR
When 0 is written in RDRF after reading RDRF = 1
When ICDRR is read with an instruction
Rev. 1.00 Aug. 28, 2006 Page 253 of 400
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C Bus Interface 2 (IIC2)
2
C bus
REJ09B0268-0100