C Bus Status Register (Icsr) - Renesas Hitachi H8S/2194 Series Hardware Manual

2
25.2.6 I

C Bus Status Register (ICSR)

Bit : 7
ESTP
Initial value :
0
R/(W) *
R/W :
Note: * Only 0 can be written to clear the flag.
ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge
confirmation and control.
ICSR is initialized to H'00 by a reset.
Bit 7: Error Stop Condition Detection Flag (ESTP)
Indicates that a stop condition has been detected during frame transfer in I
mode.
Bit 7
ESTP Description
0 No error stop condition
[Clearing condition]
(1) When 0 is written in ESTP after reading ESTP = 1
(2) When the IRIC flag is cleared to 0
T
2
1 In I C bus format slave mode
Error stop condition detected
[Setting condition]
• When a stop condition is detected during frame transfer
T
In other modes
No meaning
Rev. 2.0, 11/00, page 538 of 1037
6 5
STOP IRTR AASX
0 0
R/(W) * R/(W) * R/(W) *
4 3 2
AL AAS
0 0 0
R/(W) * R/(W) *
1 0
ADZ ACKB
0 0
R/(W) *
R/W
2
C bus format slave
(Initial value)