I 2 C Bus Status Register (Icsr) - Renesas H8S/2158 User Manual

2
Section 17 I C Bus Interface (IIC)
2
17.3.6 I C Bus Status Register (ICSR)
ICSR consists of status flags. Also see table 17.4.
Bit Initial
Bit Name Value
7 ESTP 0
6 STOP 0
5 IRTR 0
Rev. 3.00 Jan 25, 2006 page 492 of 872
REJ09B0286-0300
R/W Description
R/(W) * Error Stop Condition Detection Flag
This bit is valid in I
[Setting condition]
•
When a stop condition is detected during frame transfer.
[Clearing conditions]
•
When 0 is written in ESTP after reading ESTP = 1
•
When the IRIC flag in ICCR is cleared to 0
R/(W) * Normal Stop Condition Detection Flag
This bit is valid in I
[Setting condition]
•
When a stop condition is detected during frame transfer.
[Clearing conditions]
•
When 0 is written in STOP after reading STOP = 1
•
When the IRIC flag in ICCR is cleared to 0
R/(W) * I 2
C Bus Interface Continuous Transfer Interrupt Request Flag
Indicates that the IIC module has issued an interrupt request to
the CPU, and the source is completion of reception/transmission
of one frame in continuous transmission/reception for which DTC
activation is possible. When the IRTR flag is set to 1, the IRIC
flag is also set to 1 at the same time.
[Setting condition in I
•
When the ICDRE or ICDRF flag in ICXR is set to 1 when
AASX = 1
[Setting condition in I
mode]
•
When the ICDRE or ICDRF flag in ICXR is set to 1
[Clearing conditions]
•
When 0 is written in IRTR after reading IRTR = 1
•
When the IRIC flag in ICCR is cleared to 0 (while ICE = 1 or
ICXE = 1)
2
C bus format slave mode.
2
C bus format slave mode.
2
C bus format slave mode]
2
C bus format modes other than slave