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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
Appendix 2.2 Differences between M16C/26A Group and M16C/26 Group
Item
Clock Generation
Circuit
System Clock
Source After Reset
(Initial value of the CM21
bit in the CM2 register)
On-chip Oscillator Clock Selectable (8MHz/1MHz/500KHz)
PACR2 to PACR0 in Necessary to set after reset
the PACR register
IFSR20 bit in the
IFSR2A register
External Interrupt
13 pin (48-pin version)
Function
P7
, P7
0
1
A/D Input Pin
(48-pin version)
A/D operation Mode 8 modes (single, repeat, single sweep,
Timer B Operation
Mode
CRC Calculation
Three-phase motor
Control
Digital Debounce
Function
3 pin (48-pin version)
function
UART1 Compatible Switching to P6
pin
Flash Memory
Protect Function
Package
NOTE:
1. Since the emulator between the M16C/26A Group and M16C/29 Group are the same, all functions of
M16C/29 are built in the emulator. When evaluating M16C/26A Group, do not access to the SFR which
is not built in M16C/26A Group. Refer to Hardware Manual about detail and electrical characteristics.
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
M16C/26A Group
4 circuits (Main clock oscillation circuit,
Sub clock oscillation circuit,
on-chip oscillator,
PLL frequency synthesizer)
On-chip oscillator
(Initial value "1" of CM21 bit)
48pin:"100
", 42pin:"001
2
Necessary to set to "1" after reset
________
8 causes (INT2 added)
________
P8
/INT2/ZP
4
N-ch open drain output and CMOS
output are selectable by S/W
12 channels
repeat sweep mode 0, repeat sweep
mode 1, simultaneous sampling,
delayed trigger mode 0, delayed
trigger mode 1)
1 shunt current measurement function
is available
5 modes (timer, event counter, pulse
periods measurement, pulse width
measurment, A/D trigger)
1 shunt current measurement function
is available
Available (compatible to CRC-CCITT
and CRC-16 methods)
•Waveform output/Switching port output •Waveform output/Switching port output
by software is enabled
•Position data retention function
This function is in the NMI/SD pin and
________
INT5 pin
P9
/CLK
/TB0
/AN3
0
OUT
IN
(CLK
: f1, f8, f32, and f
OUT
to P6
4
is enabled
Protection to blocks 0, 1 by FMR02 bit
Protection to the blocks 0 to 3 by
FMR16 bit
PLQP0048KB-A(48P6Q), PRSP0042GA-B(42P2R)
page 327
f o
3
2
9
6
C
2 /
6
) T
3 circuits (Main clock oscillation circuit,
Main clock
(Initial value "0" of CM21 bit)
Fixed (1MHz)
No PACR register
"
2
No IFSR2A register
7 causes
IV
N-ch open drain output
8 channels
5 modes (single, repeat, single sweep,
repeat sweep mode 0, repeat sweep
mode 1)
4 modes (timer, event counter, pulse
periods measurement, pulse width
measurment)
Not available
by software is disabled
•No position data retention function
_______ _____
Not available
P9
0
output)
C
or P7
to P7
P6
7
0
3
Protection to blocks 0,1 by FMR02 bit
PLQP0048KB-A(48P6Q)
Appendix 2. Functional Difference
M16C/26 Group
Sub clock oscillation circuit,
on-chip oscillator)
CC
/TB0
0
IN
to P6
4
7
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