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EPn Receive Configuration and Status (Host) Register
The
USB_EPI[N]_RXCSR_H
currently selected receive endpoint.
AUTOCLR (R/W)
Auto Clear Enable
AUTOREQ (R/W)
Auto Request Clear Enable
DMAREQEN (R/W)
DMA Request Enable Rx EP
PIDERR (R/W0C)
Packet ID Error
DMAREQMODE (R/W)
DMA Mode Select
DATGLEN (R/W)
Data Toggle Write Enable
DATGL (R/W)
Data Toggle
INCOMPRX (R/W)
Incomplete Rx
Figure 27-57: USB_EPI[N]_RXCSR_H Register Diagram
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register provides (in host mode) control and status bits for transfers through the
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
ADSP-SC58x USB Register Descriptions
RXPKTRDY (R/W0C)
Rx Packet Ready
FIFOFULL (R)
FIFO Full
RXTOERR (R/W0C)
Rx Timeout Error
NAKTODERR (R/W0C)
NAK Timeout Data Error
FLUSHFIFO (R/W)
Flush Endpoint FIFO
REQPKT (R/W)
Request Packet
RXSTALL (R/W0C)
Rx STALL
CLRDATATGL (R/W)
Clear Endpoint Data Toggle
27–117
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