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20.7
System Clock Output Disabling Function
Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCRH. When the
PSTOP bit is set to 1, output of the system clock halts and the φ pin is placed in the high-
impedance state. Figure 20.3 shows the timing of the stopping and starting of system clock output.
When the PSTOP bit is cleared to 0, output of the system clock is enabled. Table 20.4 indicates
the state of the φ pin in various operating states.
MSTCRH write cycle
(PSTOP = 1)
T1
φ pin
Figure 20.3 Starting and Stopping of System Clock Output
Table 20.4 φ φ φ φ Pin State in Various Operating States
Operating State
Hardware standby
Software standby
Sleep mode
Normal operation
T2
T3
High impedance
PSTOP = 0
High impedance
Always high
System clock output
System clock output
Section 20 Power-Down State
MSTCRH write cycle
(PSTOP = 0)
T1
T2
PSTOP = 1
High impedance
High impedance
High impedance
High impedance
Rev. 4.00 Jan 26, 2006 page 693 of 938
T3
REJ09B0276-0400
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