Clock Output Control; Figure 12.30 Sample Reception Flowchart; Figure 12.31 Clock Output Fixing Timing - Renesas H8SX/1520 Series Hardware Manual

Section 12 Serial Communication Interface (SCI)
12.7.8

Clock Output Control

Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set
to 1. Specifically, the minimum width of a clock pulse can be specified.
Figure 12.31 shows an example of clock output fixing timing when the CKE0 bit is controlled
with GM = 1 and CKE1 = 0.
CKE0
SCK
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Start
Initialization
Start reception
ORER = 0
and PER = 0?
Yes
No
RDRF = 1?
Yes
Read data from RDR and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0

Figure 12.30 Sample Reception Flowchart

Given pulse width

Figure 12.31 Clock Output Fixing Timing

No
Error processing
Given pulse width