Clock Output Control; Figure 14.30 Example Of Reception Processing Flow; Figure 14.31 Timing For Fixing Clock Output Level - Renesas H8S/2368 Series Hardware Manual

14.7.8

Clock Output Control

When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and
CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width.
Figure 14.31 shows the timing for fixing the clock output level. In this example, GM is set to 1,
CKE1 is cleared to 0, and the CKE0 bit is controlled.
CKE0
SCK
Start
Initialization
Start reception
ORER = 0 and
PER = 0
Yes
No
RDRF = 1?
Yes
Read RDR and clear
RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit to 0

Figure 14.30 Example of Reception Processing Flow

Specified pulse width

Figure 14.31 Timing for Fixing Clock Output Level

No
Error processing
Specified pulse width
Rev. 2.00, 05/03, page 575 of 820