Clock Output Control; Figure 16.33 Sample Reception Flowchart - Renesas H8S/2158 User Manual

Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
No
No
16.7.8

Clock Output Control

Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set
to 1. Specifically, the minimum width of a clock pulse can be specified.
Figure 16.34 shows an example of clock output fixing timing when the CKE0 bit is controlled
with GM = 1 and CKE1 = 1.
Rev. 3.00 Jan 25, 2006 page 454 of 872
REJ09B0286-0300
Start
Initialization
Start reception
ORER = 0
and PER = 0?
Yes
RDRF = 1 ?
Yes
Read data from RDR and
clear RDRF flag in SSR to 0
All data received?
Yes
Clear RE bit in SCR to 0
End

Figure 16.33 Sample Reception Flowchart

No
Error processing