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13.7.8
Clock Output Control
Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set
to 1. Specifically, the minimum width of a clock pulse can be specified.
Figure 13.31 shows an example of clock output fixing timing when the CKE0 bit is controlled
with GM = 1 and CKE1 = 0.
CKE0
SCK
Start
Initialization
Start reception
ORER = 0
and PER = 0?
Yes
No
RDRF = 1 ?
Yes
Read data from RDR and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
Figure 13.30 Sample Reception Flowchart
Given pulse width
Figure 13.31 Clock Output Fixing Timing
Section 13 Serial Communication Interface (SCI)
No
Error processing
Given pulse width
Rev.2.00 Jun. 28, 2007 Page 515 of 666
REJ09B0311-0200
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