Module Stop Mode; Clock Output Control; Figure 22.3 Hardware Standby Mode Timing - Renesas H8S/2437 Hardware Manual

Oscillator
22.2.5

Module Stop Mode

Module stop mode can be set for individual on-chip peripheral modules.
When the corresponding MSTP bit in MSTPCR or EXMSTPCR is set to 1, module operation
stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues
operating independently.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the PWM, PWMX, SCI, and IIC3 are retained.
After reset clearance, all modules are in module stop mode.
The module registers which are set in module stop mode cannot be read or written to.
φ φ φ φ Clock Output Control
22.3
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 22.3 shows the state of the φ pin in each processing state.

Figure 22.3 Hardware Standby Mode Timing

Oscillation Reset
stabilization exception
time handling
Rev. 1.00, 09/03, page 631 of 704