Spi Slave - Altera cyclone V Technical Reference

19-12
Master Microwire Serial Transfers
The receive FIFO threshold level (
buffer is nearly full. When a DMA is used, the receive data level (DMARDLR) can be used to early request
the DMA Controller, indicating that the receive FIFO buffer is nearly full. †
Related Information
Motorola SPI Protocol
•
• Texas Instruments Synchronous Serial Protocol (SSP)
• SPI Controller Address Map and Register Definitions
Master Microwire Serial Transfers
"National Semiconductor Microwire Protocol" describes the Microwire serial protocol in detail. †
Microwire serial transfers from the SPI serial master are controlled by the Microwire Control Register
( ). The MHS bit field enables and disables the Microwire handshaking interface. The
MWCR
controls the direction of the data frame (the control frame is always transmitted by the master and
received by the slave). The
All Microwire transfers are started by the SPI serial master when there is at least one control word in the
transmit FIFO buffer and a slave is enabled. When the SPI master transmits the data frame (
transfer is terminated by the shift logic when the transmit FIFO buffer is empty. When the SPI master
receives the data frame (
field. If the transfer is nonsequential (
after shifting in the data frame from the slave. When the transfer is sequential (
by the shift logic when the number of data frames received is equal to the value in the
one. †
When the handshaking interface on the SPI master is enabled (
polled after transmission. Only when the slave reports a ready status does the SPI master complete the
transfer and clear its
the slave device returns a ready status. †
Related Information
National Semiconductor Microwire Protocol

SPI Slave

The SPI slave handles serial communication with transfer initiated and controlled by serial master
peripheral devices.
•
sclk_in
•
ss_in_n
•
ss_oe_n
• —transmit data line for the SPI master or slave †
txd
• —receive data line for the SPI master or slave †
rxd
When the SPI serial slave is selected, it enables its
from the serial slave are regulated on the serial clock line (
Data are propagated from the serial slave on one edge of the serial clock line and sampled on the opposite
edge. †
When the SPI serial slave is not selected, it must not interfere with data transfers between the serial-master
and other serial-slave devices. When the serial slave is not selected, its
high impedance drive onto the SPI master
external to the SPI controller.
Altera Corporation
RXF TLR
on page 19-16
bit field defines whether the transfer is sequential or nonsequential. †
MWMOD
= 1), the termination of the transfer depends on the setting of the
MDD
status. If the transfer is continuous, the next control/data frame is not sent until
BUSY
—serial clock to the SPI slave †
—slave select input to the SPI slave †
—output enable for the SPI master or slave †
spi_oe_n
) can be used to give early indication that the receive FIFO
on page 19-18
on page 19-33
= 0), it is terminated when the transmit FIFO buffer is empty
MWMOD
on page 19-19
data onto the serial bus. All data transfers to and
txd
sclk_in
line. The buffers shown in the
rxd
is the SPI slave output enable signal. †
= 1), it is terminated
MWMOD
CTRLR1
=1), the status of the target slave is
MHS
), driven from the SPI master device.
output is buffered, resulting in a
txd
Figure 19-5
cv_5v4
2016.10.28
bit field
MDD
=1), the
MDD
bit
MWMOD
register plus
figure are
SPI Controller
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