Timer Counter Control Register (Tccr) - Renesas H8SX/1650 Hardware Manual

11.3.5

Timer Counter Control Register (TCCR)

TCCR selects the TCNT internal clock source and controls external reset input.
Bit 7
Bit Name
Initial Value 0
R/W
R/W
Bit Bit Name

7 to 4
3 TMRIS

2
1 ICKS1
0 ICKS0
6 5
0 0
R/W R/W
Initial
Value R/W Description
0 R/W Reserved
These bits are always read as 0. The write value should
always be 0.
0 R/W Timer Reset Input Select
Selects an external reset input when the CCLR1 and
CCLR0 bits in TCR are B'11.
0: Cleared at rising edge of the external reset
1: Cleared when the external reset is high
0 R/W Reserved
This bit is always read as 0. The write value should
always be 0
0 R/W Internal Clock Select 1 and 0
0 R/W These bits in combination with bits CKS2 to CKS0 in TCR
select the internal clock. See table 11.2.
4 3
TMRIS
0 0
R/W R/W
Rev.2.00 Jun. 28, 2007 Page 419 of 666
Section 11 8-Bit Timers (TMR)
2 1
ICKS1 ICKS0
0 0
R/W R/W
REJ09B0311-0200
0
0
R/W