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3.2.4 FIFO control register
This register (FCR: 5000_000CH (UART0), 5001_000CH (UART1), 5002_000CH (UART2)) controls the
transmit/receive FIFO.
15
14
7
6
Receiver Trigger
Name
R/W
Reserved
R
Receiver Trigger *
R/W
64 Byte FIFO Enable
R/W
*
Reserved
R/W
DMA Mode Select *
R/W
Transmitter FIFO
R/W
Reset
Receiver FIFO Reset
R/W
FIFO Enable *
R/W
18
CHAPTER 3 REGISTERS
13
12
Reserved
5
4
64 Byte FIFO
Reserved
Enabled
Bit
After Reset
15:8
0
Reserved. When these bits are read, 0 is returned for each bit.
7:6
00
Valid only in FIFO mode (bit 0 of FCR register = 1).
Specifies the threshold (trigger level) of data stored in the receive
FIFO in order to issue an interrupt request or a reception DMA
request.
In 16-byte FIFO mode (bit 5 of FCR register = 0)
00: 1 byte
10: 8 bytes
In 64-byte FIFO mode (bit 5 of FCR register = 1)
00: 1 byte
10: 32 bytes
5
0
Valid only in FIFO mode (bit 0 of FCR register = 1).
Specifies the FIFO capacity.
0: 16 bytes (16550 mode)
4
0
Reserved. Written data is ignored.
3
0
Specifies the DMA mode in FIFO mode. The DMA mode is specified
by setting this bit with bits 3 and 2 of the HCR0 register.
2
0
Setting this bit to 1 generates a synchronization reset pulse (1
VBCLK cycle) and resets the transmit FIFO and FIFO address
counter. This bit is automatically reset to 0.
Caution The transmit shift register (TSR) is not reset. If a
1
0
Setting this bit to 1 generates a synchronization reset pulse (1
VBCLK cycle) and resets the receive FIFO and FIFO address
counter. This bit is automatically reset to 0.
Caution The receive shift register (RSR) is not reset. If a
0
0
Selects the FIFO operating mode.
0: Non-FIFO mode (16450 mode)
1: 16-/64-byte FIFO mode (selected by bit 5 of the FCR register)
User's Manual S19262EJ3V0UM
11
10
3
2
DMA Mode
Transmitter
Select
FIFO Reset
Function
01: 4 bytes
11: 14 bytes
01: 16 bytes
11: 56 bytes
1: 64 bytes
reset occurs during transmission, one frame that
has only zeros might be transmitted after the data in
the TSR register has been transmitted.
reset occurs during reception, data being received is
correctly stored in the receive FIFO after the reset.
9
8
1
0
Receiver FIFO
FIFO Enable
Reset
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