I 2 C0 Control Register 1 (S3D0 Register); Bit 0 : Interrupt Enable Bit By Stop Condition (Sim ); Bit 1: Interrupt Enable Bit At The Completion Of Data Receive (Wit) - Renesas M16C/29 Series User Manual

M 1 6 C 2 / 9 G o r u p
2
16.6 I C0 Control Register 1 (S3D0 register)
The S3D0 register controls the I

16.6.1 Bit 0 : Interrupt Enable Bit by STOP Condition (SIM )

The SIM bit enables the I
2
is set to 1, the I
change in the PIN flag).

16.6.2 Bit 1: Interrupt Enable Bit at the Completion of Data Receive (WIT)

If the WIT bit is set to 1 while the ACK-CLK bit in the S20 register is set to 1 (ACK clock), the I
interface interrupt request is generated and the PIN bit is set to 1 at the falling edge of the last data bit
clock. Then an "L" signal is applied to the SCL
and Figure 16.12 show the interrupt generation timing and the procedure of communication restart. After
the communication is restarted, the PIN bit is set to 0 again, synchronized with the falling edge of the ACK
2
clock, and the I
Table16.4 Timing of Interrupt Generation in Data Receive Mode
2
I C bus Interface Interrupt Generation Timing
1) Synchronized with the falling edge of the
last data bit clock
2) Synchronized with the falling edge of the
ACK clock
The internal WAIT flag can be read by reading the WIT bit. The internal WAIT flag is set to 1 after writing
data to the S00 register and it is set to 0 after writing to the S20 register.
Consequently, the I
(See Figure 16.12)
When the data is transmitted and the address data is received immediately after the START condition,
the WAIT flag remains 0 regardless of the WIT bit setting, and the I
only generated at the falling edge of the ACK clock. Set the WIT bit to 0 when the ACK-CLK bit in the S20
register is set to 0 (no ACK clock).
R e . v 1 1 . 2 M r a 3 . , 0 2 0 0 7
R E J 0 9 B 0 1 0 1 0 - 1 1 2
2
C bus interface circuit.
2
C bus interface interrupt request by detecting a STOP condition. If the SIM bit
C bus interface interrupt request is generated by the STOP condition detect (no need to
C bus interface interrupt request is generated.
2
C bus interface interrupt request generated by the timing 1) or 2) can be determined.
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16. MULTI-MASTER I
and the ACK clock generation is controlled. Table 16.4
MM
Procedure of Communication Restart
Set the ACK bit in the S20 register.
Set the PIN bit to 1.
(Do not write to the S00 register. The ACK clock
operation may be unstable.)
Set the S00 register
2
C bus INTERFACE
2
C bus interface interrupt request is
2
C bus