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Renesas H8S/2357 Series Manuals
Manuals and User Guides for Renesas H8S/2357 Series. We have
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Renesas H8S/2357 Series manual available for free PDF download: Hardware Manual
Renesas H8S/2357 Series Hardware Manual (1047 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 4.54 MB
Table of Contents
Table of Contents
13
Section 1 Overview
29
Overview
29
Block Diagram
34
Pin Description
35
Pin Arrangement
35
Pin Functions in each Operating Mode
39
Pin Functions
43
Section 2 CPU
49
Overview
49
Features
49
Differences between H8S/2600 CPU and H8S/2000 CPU
50
Differences from H8/300 CPU
50
Differences from H8/300H CPU
51
CPU Operating Modes
51
Advanced Mode
51
Address Space
54
Register Configuration
55
Overview
55
General Registers
55
Control Registers
56
Initial Register Values
57
Data Formats
58
General Register Data Formats
58
Memory Data Formats
60
Instruction Set
61
Overview
61
Instructions and Addressing Modes
62
Table of Instructions Classified by Function
63
Basic Instruction Formats
69
Addressing Modes and Effective Address Calculation
69
Addressing Mode
69
Effective Address Calculation
72
Processing States
75
Overview
75
Reset State
76
Exception-Handling State
76
Program Execution State
78
Bus-Released State
78
Power-Down State
78
Basic Timing
79
Overview
79
On-Chip Memory (ROM, RAM)
79
On-Chip Supporting Module Access Timing
80
External Address Space Access Timing
81
Usage Note
81
TAS Instruction
81
Section 3 MCU Operating Modes
83
Overview
83
Operating Mode Selection (H8S/2357 F-ZTAT Only)
83
Operating Mode Selection (ZTAT, Masked ROM, Romless Version, and H8S/2398 F-ZTAT)
84
Register Configuration
85
Register Descriptions
85
Mode Control Register (MDCR)
85
System Control Register (SYSCR)
85
System Control Register 2 (SYSCR2) (F-ZTAT Version Only)
86
Operating Mode Descriptions
88
Mode 1
88
Mode 2 (H8S/2398 F-ZTAT Only)
88
Mode 3 (H8S/2398 F-ZTAT Only)
88
Mode 4 (On-Chip ROM Disabled Expansion Mode)
88
Mode 5 (On-Chip ROM Disabled Expansion Mode)
88
Mode 6 (On-Chip ROM Enabled Expansion Mode)
88
Mode 7 (Single-Chip Mode)
89
Modes 8 and 9
89
Mode 10 (H8S/2357 F-ZTAT Only)
89
Mode 11 (H8S/2357 F-ZTAT Only)
89
Modes 12 and 13 (H8S/2357 F-ZTAT Only)
89
Mode 14 (H8S/2357 F-ZTAT Only)
89
Mode 15 (H8S/2357 F-ZTAT Only)
89
Pin Functions in each Operating Mode
90
Memory Map in each Operating Mode
90
Section 4 Exception Handling
99
Overview
99
Exception Handling Types and Priority
99
Exception Handling Operation
100
Exception Vector Table
100
Reset
102
Overview
102
Reset Types
102
Reset Sequence
103
Interrupts after Reset
104
State of On-Chip Supporting Modules after Reset Release
104
Traces
104
Interrupts
105
Trap Instruction
106
Stack Status after Exception Handling
106
Notes on Use of the Stack
107
Section 5 Interrupt Controller
109
Overview
109
Features
109
Block Diagram
110
Pin Configuration
110
Register Configuration
111
Register Descriptions
111
System Control Register (SYSCR)
111
Interrupt Priority Registers a to K (IPRA to IPRK)
112
IRQ Enable Register (IER)
113
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
114
IRQ Status Register (ISR)
114
Interrupt Sources
115
External Interrupts
115
Internal Interrupts
116
Interrupt Exception Handling Vector Table
116
Interrupt Operation
119
Interrupt Control Modes and Interrupt Operation
119
Interrupt Control Mode 0
121
Interrupt Control Mode 2
123
Interrupt Exception Handling Sequence
125
Interrupt Response Times
126
Usage Notes
127
Contention between Interrupt Generation and Disabling
127
Instructions that Disable Interrupts
127
Times When Interrupts Are Disabled
128
Interrupts During Execution of EEPMOV Instruction
128
DTC and DMAC Activation by Interrupt
128
Overview
128
Block Diagram
129
Operation
129
Note on Use
130
Section 6 Bus Controller
131
Overview
131
Features
131
Block Diagram
133
Pin Configuration
134
Register Configuration
135
Register Descriptions
136
Bus Width Control Register (ABWCR)
136
Access State Control Register (ASTCR)
137
Wait Control Registers H and L (WCRH, WCRL)
138
Bus Control Register H (BCRH)
141
Bus Control Register L (BCRL)
142
Memory Control Register (MCR)
144
DRAM Control Register (DRAMCR)
146
Refresh Timer/Counter (RTCNT)
147
Refresh Time Constant Register (RTCOR)
148
Overview of Bus Control
149
Area Partitioning
149
Bus Specifications
150
Memory Interfaces
151
Advanced Mode
151
Chip Select Signals
152
Basic Bus Interface
153
Overview
153
Data Size and Data Alignment
153
Valid Strobes
155
Basic Timing
156
Wait Control
164
DRAM Interface
166
Overview
166
Setting DRAM Space
166
Address Multiplexing
166
Data Bus
166
Pins Used for DRAM Interface
167
Basic Timing
168
Precharge State Control
169
Wait Control
169
Byte Access Control
171
Burst Operation
172
Refresh Control
175
DMAC Single Address Mode and DRAM Interface
177
When DDS = 1
177
When DDS = 0
178
Burst ROM Interface
178
Overview
178
Basic Timing
179
Wait Control
180
Idle Cycle
181
Operation
181
Usage Notes
183
Pin States in Idle Cycle
185
Write Data Buffer Function
186
Bus Release
187
Overview
187
Operation
187
Pin States in External Bus Released State
188
Transition Timing
189
Usage Note
189
Bus Arbitration
190
Overview
190
Operation
190
Bus Transfer Timing
191
External Bus Release Usage Note
191
Resets and the Bus Controller
192
Section 7 DMA Controller
193
Overview
193
Features
193
Block Diagram
194
Overview of Functions
195
Pin Configuration
197
Register Configuration
198
Register Descriptions (1) (Short Address Mode)
199
Memory Address Registers (MAR)
200
I/O Address Register (IOAR)
200
Execute Transfer Count Register (ETCR)
201
DMA Control Register (DMACR)
202
DMA Band Control Register (DMABCR)
205
Register Descriptions (2) (Full Address Mode)
209
Memory Address Register (MAR)
209
I/O Address Register (IOAR)
209
Execute Transfer Count Register (ETCR)
209
DMA Control Register (DMACR)
211
DMA Band Control Register (DMABCR)
214
Register Descriptions (3)
218
DMA Write Enable Register (DMAWER)
218
DMA Terminal Control Register (DMATCR)
220
Module Stop Control Register (MSTPCR)
221
Operation
222
Transfer Modes
222
Sequential Mode
224
Idle Mode
227
Repeat Mode
229
Single Address Mode
232
Normal Mode
235
Block Transfer Mode
238
DMAC Activation Sources
243
Basic DMAC Bus Cycles
245
DMAC Bus Cycles (Dual Address Mode)
246
DMAC Bus Cycles (Single Address Mode)
254
Write Data Buffer Function
258
DMAC Multi-Channel Operation
259
Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC
260
NMI Interrupts and DMAC
261
Forced Termination of DMAC Operation
262
Clearing Full Address Mode
263
Interrupts
264
Usage Notes
265
Section 8 Data Transfer Controller
269
Overview
269
Features
269
Block Diagram
270
Register Configuration
271
Register Descriptions
272
DTC Mode Register a (MRA)
272
DTC Mode Register B (MRB)
273
DTC Source Address Register (SAR)
274
DTC Destination Address Register (DAR)
274
DTC Transfer Count Register a (CRA)
274
DTC Transfer Count Register B (CRB)
274
DTC Enable Registers (DTCER)
275
DTC Vector Register (DTVECR)
275
Module Stop Control Register (MSTPCR)
276
Operation
277
Overview
277
Activation Sources
279
DTC Vector Table
280
Location of Register Information in Address Space
283
Normal Mode
284
Repeat Mode
285
Block Transfer Mode
286
Chain Transfer
287
Operation Timing
288
Number of DTC Execution States
289
Procedures for Using DTC
290
Examples of Use of the D7TC
290
Interrupts
292
Usage Notes
292
Section 9 I/O Ports
293
Overview
293
Port1
297
Overview
297
Register Configuration
297
Pin Functions
299
Port2
307
Overview
307
Register Configuration
307
Pin Functions
309
Port 3
317
Overview
317
Register Configuration
317
Pin Functions
319
Port 4
321
Overview
321
Register Configuration
321
Pin Functions
321
Port 5
322
Overview
322
Register Configuration
322
Pin Functions
324
Port 6
325
Overview
325
Register Configuration
325
Pin Functions
327
Port a
329
Overview
329
Register Configuration
330
Pin Functions
332
MOS Input Pull-Up Function (On-Chip ROM Version Only)
334
Port B
335
Overview
335
Register Configuration (On-Chip ROM Version Only)
336
Pin Functions
338
MOS Input Pull-Up Function (On-Chip ROM Version Only)
339
Port C
340
Overview
340
Register Configuration (On-Chip ROM Version Only)
341
Pin Functions
343
MOS Input Pull-Up Function (On-Chip ROM Version Only)
344
Port D
345
Overview
345
Register Configuration (On-Chip ROM Version Only)
346
Pin Functions
348
MOS Input Pull-Up Function (On-Chip ROM Version Only)
349
Port E
350
Overview
350
Register Configuration
351
Pin Functions
353
MOS Input Pull-Up Function (On-Chip ROM Version Only)
354
Port F
355
Overview
355
Register Configuration
356
Pin Functions
358
Port G
360
Overview
360
Register Configuration
360
Pin Functions
363
Section 10 16-Bit Timer Pulse Unit (TPU)
365
Overview
365
Features
365
Block Diagram
369
Pin Configuration
370
Register Configuration
371
Register Descriptions
373
Timer Control Register (TCR)
373
Timer Mode Register (TMDR)
377
Timer I/O Control Register (TIOR)
379
Timer Interrupt Enable Register (TIER)
389
Timer Status Register (TSR)
391
Timer Counter (TCNT)
394
Timer General Register (TGR)
394
Timer Start Register (TSTR)
394
Timer Synchro Register (TSYR)
395
Module Stop Control Register (MSTPCR)
396
Interface to Bus Master
397
16-Bit Registers
397
8-Bit Registers
398
Operation
399
Overview
399
Basic Functions
400
Synchronous Operation
405
Buffer Operation
407
Cascaded Operation
410
PWM Modes
411
Phase Counting Mode
416
Interrupts
422
Interrupt Sources and Priorities
422
DTC/DMAC Activation
424
A/D Converter Activation
424
Operation Timing
425
Input/Output Timing
425
Interrupt Signal Timing
429
Usage Notes
432
Section 11 Programmable Pulse Generator (PPG)
439
Overview
439
Features
439
Block Diagram
440
Pin Configuration
441
Registers
442
Register Descriptions
443
Next Data Enable Registers H and L (NDERH, NDERL)
443
Output Data Registers H and L (PODRH, PODRL)
444
Next Data Registers H and L (NDRH, NDRL)
444
Notes on NDR Access
444
PPG Output Control Register (PCR)
446
PPG Output Mode Register (PMR)
447
Port 1 Data Direction Register (P1DDR)
449
Port 2 Data Direction Register (P2DDR)
449
Module Stop Control Register (MSTPCR)
450
Operation
451
Overview
451
Output Timing
452
Normal Pulse Output
453
Non-Overlapping Pulse Output
454
Inverted Pulse Output
457
Pulse Output Triggered by Input Capture
458
Usage Notes
459
Section 12 8-Bit Timers
461
Overview
461
Features
461
Block Diagram
462
Pin Configuration
463
Register Configuration
463
Register Descriptions
464
Timer Counters 0 and 1 (TCNT0, TCNT1)
464
Time Constant Registers A0 and A1 (TCORA0, TCORA1)
464
Time Constant Registers B0 and B1 (TCORB0, TCORB1)
465
Time Control Registers 0 and 1 (TCR0, TCR1)
465
Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1)
467
Module Stop Control Register (MSTPCR)
469
Operation
470
TCNT Incrementation Timing
470
Compare Match Timing
471
Timing of External RESET on TCNT
472
Timing of Overflow Flag (OVF) Setting
472
Operation with Cascaded Connection
473
Interrupts
474
Interrupt Sources and DTC Activation
474
A/D Converter Activation
474
Sample Application
475
Usage Notes
476
Contention between TCNT Write and Clear
476
Contention between TCNT Write and Increment
477
Contention between TCOR Write and Compare Match
478
Contention between Compare Matches a and B
478
Switching of Internal Clocks and TCNT Operation
479
Interrupts and Module Stop Mode
480
Section 13 Watchdog Timer
481
Overview
481
Features
481
Block Diagram
482
Pin Configuration
482
Register Configuration
483
Register Descriptions
484
Timer Counter (TCNT)
484
Timer Control/Status Register (TCSR)
484
Reset Control/Status Register (RSTCSR)
485
Notes on Register Access
487
Operation
488
Watchdog Timer Operation
488
Interval Timer Operation
489
Timing of Setting Overflow Flag (OVF)
489
Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
490
Interrupts
490
Usage Notes
491
Contention between Timer Counter (TCNT) Write and Increment
491
Changing Value of CKS2 to CKS0
491
Switching between Watchdog Timer Mode and Interval Timer Mode
491
System Reset by WDTOVF Signal
491
Internal Reset in Watchdog Timer Mode
492
Section 14 Serial Communication Interface (SCI)
493
Overview
493
Features
493
Block Diagram
495
Pin Configuration
495
Register Configuration
496
Register Descriptions
497
Receive Shift Register (RSR)
497
Receive Data Register (RDR)
497
Transmit Shift Register (TSR)
497
Transmit Data Register (TDR)
498
Serial Mode Register (SMR)
498
Serial Control Register (SCR)
500
Serial Status Register (SSR)
503
Bit Rate Register (BRR)
506
Smart Card Mode Register (SCMR)
513
Module Stop Control Register (MSTPCR)
514
Operation
515
Overview
515
Operation in Asynchronous Mode
517
Multiprocessor Communication Function
527
Operation in Clocked Synchronous Mode
533
SCI Interrupts
540
Usage Notes
542
Section 15 Smart Card Interface
545
Overview
545
Features
545
Block Diagram
546
Pin Configuration
546
Register Configuration
547
Register Descriptions
548
Smart Card Mode Register (SCMR)
548
Serial Status Register (SSR)
549
Serial Mode Register (SMR)
550
Serial Control Register (SCR)
551
Operation
552
Overview
552
Pin Connections
552
Data Format
553
Register Settings
554
Clock
555
Data Transfer Operations
557
Operation in GSM Mode
562
Usage Notes
563
Section 16 A/D Converter
567
Overview
567
Features
567
Block Diagram
568
Pin Configuration
568
Register Configuration
569
Register Descriptions
570
A/D Data Registers a to D (ADDRA to ADDRD)
570
A/D Control/Status Register (ADCSR)
570
A/D Control Register (ADCR)
572
Module Stop Control Register (MSTPCR)
573
Interface to Bus Master
574
Operation
574
Single Mode (SCAN = 0)
574
Scan Mode (SCAN = 1)
576
Input Sampling and A/D Conversion Time
577
External Trigger Input Timing
578
Interrupts
578
Usage Notes
579
Section 17 D/A Converter
583
Overview
583
Features
583
Block Diagram
583
Pin Configuration
584
Register Configuration
584
Register Descriptions
585
D/A Data Registers 0 and 1 (DADR0, DADR1)
585
D/A Control Register (DACR)
585
Module Stop Control Register (MSTPCR)
586
Operation
587
Section 18 RAM
589
Overview
589
Block Diagram
589
Register Configuration
589
Register Descriptions
590
System Control Register (SYSCR)
590
Operation
590
Usage Note
590
Section 19 ROM
591
Overview
591
Block Diagram
591
Register Configuration
591
Register Descriptions
592
Mode Control Register (MDCR)
592
Bus Control Register L (BCRL)
592
Operation
593
PROM Mode (H8S/2357 ZTAT)
594
PROM Mode Setting
594
Socket Adapter and Memory Map
595
Programming (H8S/2357 ZTAT)
597
Overview
597
Programming and Verification
598
Programming Precautions
600
Reliability of Programmed Data
601
Overview of Flash Memory (H8S/2357 F-ZTAT)
602
Features
602
Block Diagram
603
Flash Memory Operating Modes
604
Boot Mode
605
Pin Configuration
609
Register Configuration
609
Register Descriptions
610
Flash Memory Control Register 1 (FLMCR1)
610
Flash Memory Control Register 2 (FLMCR2)
612
Erase Block Registers 1 and 2 (EBR1, EBR2)
613
System Control Register 2 (SYSCR2)
614
RAM Emulation Register (RAMER)
614
On-Board Programming Modes
616
Boot Mode
616
User Program Mode
620
Programming/Erasing Flash Memory
622
Program Mode
622
Program-Verify Mode
622
Erase Mode
624
Erase-Verify Mode
624
Flash Memory Protection
626
19.10.1 Hardware Protection
626
Software Protection
627
19.10.3 Error Protection
627
Flash Memory Emulation in RAM
629
19.11.1 Emulation in RAM
629
19.11.2 RAM Overlap
630
Interrupt Handling When Programming/Erasing Flash Memory
631
Flash Memory Programmer Mode
632
19.13.1 Programmer Mode Setting
632
19.13.2 Socket Adapters and Memory Map
632
19.13.3 Programmer Mode Operation
633
Memory Read Mode
634
19.13.5 Auto-Program Mode
637
19.13.6 Auto-Erase Mode
639
19.13.7 Status Read Mode
640
Status Polling
641
19.13.9 Programmer Mode Transition Time
641
Notes on Memory Programming
642
Flash Memory Programming and Erasing Precautions
642
Overview of Flash Memory (H8S/2398 F-ZTAT)
647
19.15.1 Features
647
19.15.2 Overview
648
19.15.3 Flash Memory Operating Modes
649
19.15.4 On-Board Programming Modes
650
19.15.5 Flash Memory Emulation in RAM
652
Differences between Boot Mode and User Program Mode
653
19.15.7 Block Configuration
653
19.15.8 Pin Configuration
654
19.15.9 Register Configuration
654
Register Descriptions
655
Flash Memory Control Register 1 (FLMCR1)
655
Flash Memory Control Register 2 (FLMCR2)
657
Erase Block Register 1 (EBR1)
657
Erase Block Registers 2 (EBR2)
658
System Control Register 2 (SYSCR2)
658
RAM Emulation Register (RAMER)
659
On-Board Programming Modes
660
19.17.1 Boot Mode
661
19.17.2 User Program Mode
665
Programming/Erasing Flash Memory
666
19.18.1 Program Mode
666
19.18.2 Program-Verify Mode
666
19.18.3 Erase Mode
668
19.18.4 Erase-Verify Mode
668
Flash Memory Protection
670
19.19.1 Hardware Protection
670
Software Protection
671
19.19.3 Error Protection
672
Flash Memory Emulation in RAM
673
19.20.1 Emulation in RAM
673
19.20.2 RAM Overlap
674
Interrupt Handling When Programming/Erasing Flash Memory
675
Flash Memory Programmer Mode
675
19.22.1 Programmer Mode Setting
675
19.22.2 Socket Adapters and Memory Map
676
19.22.3 Programmer Mode Operation
678
Memory Read Mode
679
19.22.5 Auto-Program Mode
681
19.22.6 Auto-Erase Mode
683
19.22.7 Status Read Mode
684
19.22.8 Status Polling
685
19.22.9 Programmer Mode Transition Time
685
19.22.10 Notes on Memory Programming
686
Flash Memory Programming and Erasing Precautions
686
Section 20 Clock Pulse Generator
689
Overview
689
Block Diagram
689
Register Configuration
689
Register Descriptions
690
System Clock Control Register (SCKCR)
690
Oscillator
691
Connecting a Crystal Resonator
691
External Clock Input
692
Duty Adjustment Circuit
693
Medium-Speed Clock Divider
693
Bus Master Clock Selection Circuit
693
Section 21 Power-Down Modes
695
Overview
695
Register Configuration
696
Register Descriptions
697
Standby Control Register (SBYCR)
697
System Clock Control Register (SCKCR)
698
Module Stop Control Register (MSTPCR)
699
Medium-Speed Mode
700
Sleep Mode
700
Module Stop Mode
701
Usage Notes
702
Software Standby Mode
703
Clearing Software Standby Mode
703
Setting Oscillation Stabilization Time after Clearing Software Standby Mode
703
Software Standby Mode Application Example
704
Usage Notes
705
Hardware Standby Mode
706
Hardware Standby Mode Timing
706
Clock Output Disabling Function
707
Section 22 Electrical Characteristics
709
Electrical Characteristics of Masked ROM Version (H8S/2398) and Romless Versions (H8S/2394, H8S/2392, and H8S/2390)
709
Absolute Maximum Ratings
709
DC Characteristics
710
AC Characteristics
712
A/D Conversion Characteristics
729
D/A Conversion Characteristics
730
Usage Note (Internal Voltage Step down for the H8S/2398, H8S/2394, H8S/2392, and H8S/2390)
730
Electrical Characteristics of H8S/2398 F-ZTAT
731
Absolute Maximum Ratings
731
DC Characteristics
732
AC Characteristics
734
A/D Conversion Characteristics
751
D/A Conversion Characteristics
752
Flash Memory Characteristics
752
Notes on Use
755
Usage Note (Internal Voltage Step down for the H8S/2398 F-ZTAT)
755
Electrical Characteristics of H8S/2357 Masked ROM and ZTAT Versions, and H8S/2352
756
Absolute Maximum Ratings
756
DC Characteristics
756
AC Characteristics
762
A/D Conversion Characteristics
781
D/A Convervion Characteristics
782
Electrical Characteristics of H8S/2357 F-ZTAT Version
783
Absolute Maximum Ratings
783
DC Characteristics
783
AC Characteristics
787
A/D Conversion Characteristics
792
D/A Conversion Characteristics
793
Flash Memory Characteristics
793
Usage Note
796
Appendix A Instruction Set
797
Instruction List
797
Instruction Codes
820
Operation Code Map
834
Number of States Required for Instruction Execution
838
Bus States During Instruction Execution
848
Condition Code Modification
862
Appendix B Internal I/O Register
867
Addresses
867
Functions
875
Appendix C I/O Port Block Diagrams
996
Port 1 Block Diagram
996
Port 2 Block Diagram
999
Port 3 Block Diagram
1003
Port 4 Block Diagram
1006
Port 5 Block Diagram
1007
Port 6 Block Diagram
1011
Port a Block Diagram
1017
Port B Block Diagram
1020
Port C Block Diagram
1021
Port D Block Diagram
1022
Port E Block Diagram
1023
Port F Block Diagram
1024
Port G Block Diagram
1032
Appendix D Pin States
1035
Appendix E Pin States at Power-On
1039
When Pins Settle from the High-Impedance State at Power-On
1040
Appendix F Timing of Transition to and Recovery from Hardware Standby Mode
1041
Appendix F Timing of Transition to and Recovery from Hardware Standby Mode
1041
Timing of Transition to Hardware Standby Mode
1041
Appendix G Product Code Lineup
1042
Appendix H Package Dimensions
1043
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