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Freescale Semiconductor Symphony DSP56724 Reference Manual (436 pages)

Multi-Core Audio Processors

Brand: Freescale Semiconductor | Category: Processor | Size: 3 MB

Table of Contents
3
Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual

11
Chapter 1 Introduction

13
Chapter 2 Signal Descriptions

23
- Signal Groupings
  23
- Signals in each Functional Group
  27
- Power
  27
- Ground
  27
- Scan
  28
- Clock and PLL
  28
- Reset Pin
  29
- Interrupt and Mode Control
  29
- DSP Core-1 Non-Maskable Interrupt (NMI1)
  31
- Serial Host Interface (SHI and SHI_1)
  31
- Enhanced Serial Audio Interface Signals (ESAI, ESAI_1, ESAI_2, ESAI_3)
  35
- Watch Dog Timer (WDT)
  46
- External Memory Controller (EMC)
  47
- S/PDIF Audio Interface Signals
  50
- Dedicated Port G Gpios
  50
- Jtag/Once Interface Signals
  51
- Overview
  53
Chapter 3 Memory Map 3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

54
- Data and Program Memory Maps
  54
- Peripheral Register Memory Map
  55
  - Overview
    69
  - Features
    70
Chapter 4 DSP56300 Platform 4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 4.2 DSP56300 Core Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2

71
- DSP56300 Block Descriptions
  71
- Address Generation Unit (AGU)
  72
- Program Control Unit (PCU)
  73
- Once Module
  74
- Introduction
  75
Chapter 5 Core Configuration 5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 5.2 Operating Mode Register (OMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

77
- Status Register (SR)
  77
- DSP Cores Operating Modes
  80
- Interrupt Priority Registers
  83
- DMA Request Sources
  93
- Chip ID Register
  94
- Overview
  95
- Memory Map
  96
- Register Descriptions
  97
Chapter 6 Core Integration Module (CIM, CIM_1) 6.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 6.1.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2

98
- DMA Stall Register (DMAS)
  98
- Once Global Data Bus Register (OGDB)
  99
  - Introduction
    101
  - Features
    102
- External Signal Descriptions
  104
- Low Power Divider
  106
- Memory Map and Register Definition
  107
- Introduction
  113
Chapter 8 General Purpose Input/Output (GPIO) 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 8.2 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1

114
Chapter 9 Enhanced Serial Audio Interface (ESAI, ESAI_1, ESAI_2, ESAI_3)

125
- ESAI Data and Control Pins
  125
- Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2)
  126
- Receiver Serial Clock (SCKR)
  127
- Transmitter Serial Clock (SCKT)
  128
- Frame Sync for Receiver (FSR)
  129
- Frame Sync for Transmitter (FST)
  130
- ESAI Programming Model
  131
- ESAI Transmit Control Register (TCR)
  135
- ESAI Receive Clock Control Register (RCCR)
  145
- ESAI Receive Control Register (RCR)
  149
- ESAI Common Control Register (SAICR)
  154
- ESAI Status Register (SAISR)
  156
- ESAI Receive Shift Registers
  163
- Receive Slot Mask Registers (RSMA, RSMB)
  165
- Operating Modes
  166
- ESAI Interrupt Requests
  167
- Operating Modes—Normal, Network and On-Demand
  168
- Serial I/O Flags
  169
- Gpio—Pins and Registers
  170
- Port C Data Register (PDRC)
  171
- ESAI Initialization Examples
  172
- Initializing Only the ESAI Receiver Section
  173
- Internal Clock Connections between ESAI and ESAI_1, ESAI_2 and ESAI_3
  174
- Introduction
  175
Chapter 10 Serial Host Interface (SHI, SHI_1) 10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1

176
Chapter 14 Shared Bus Arbiter 14.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1

192
- Overview
  192
- SHI Programming Considerations
  194
- SPI Slave Mode
  195
- SPI Master Mode
  196
- I 2 C Master Mode
  200
- SHI Operation During DSP Stop
  201
- Introduction
  205
Chapter 11 Triple Timer Module (TEC, TEC_1) 11.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1 11.1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1

206
- Individual Timer Block Diagram
  206
- Operation
  207
- Timer Exceptions
  208
- Timer GPIO (Mode 0)
  209
- Reserved Modes
  210
- Triple Timer Module Programming Model
  211
- Timer Prescaler Load Register (TPLR)
  212
- Timer Prescaler Count Register (TPCR)
  213
- Timer Load Register (TLR)
  216
Chapter 17 EMC Burst Buffer

217
- Introduction
  217
Chapter 12 Watchdog Timer (WDT, WDT_1) 12.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1 12.2 WDT Pin-Outs for Different Device Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1

219
- WDT Registers
  219
- Watchdog Counter and WCNTR Register
  220
- Watchdog Service Register (WSR)
  221
- Watchdog Operating Modes
  222
Chapter 20 Chip Configuration Module

223
- Introduction
  223
- Features
  225
- Register Descriptions
  227
- Programming Model
  235
Chapter 13 Inter-Core Communication (ICC) 13.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1 13.1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1

236
- Inter-Core Non-Maskable Interrupts
  236
- Polling
  237
- Reset
  238
- Functional Description
  240
Chapter 16 Shared Peripheral Bus

249
- Introduction
  249
- Overview
  250
Chapter 19 Asynchronous Sample Rate Converter 19.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-1 19.1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-2

251
- Features
  251
- Read Access
  253
- Write Access
  254
Chapter 21 External Memory Controller (EMC)

257
- Introduction
  257
Chapter 22 JTAG Controller 22.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1

259
- Features
  259
- Memory Map
  260
- Register Descriptions
  261
Chapter 18 S/PDIF-Sony/Philips Digital Interface 18.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-1 18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-3

262
- Cdtext Control Register (SRCD)
  262
- Phaseconfig Register (SRPC)
  263
- S/PDIF Reception Registers
  265
- S/PDIF Transmission Registers
  267
- S/PDIF Freqmeas Register (SRFM)
  270
- S/PDIF Receiver
  271
- Channel Status Reception
  274
- Validity Flag Reception
  276
- S/PDIF Receiver Interrupt Exception Definition
  277
- Standards Compliance
  278
- Audio Data Transmission
  279
- Channel Status Transmission
  280
- Introduction
  281
Chapter 15 Shared Memory (Shared Memory)

282
- Overview
  282
- Features
  283
- Modes of Operation
  284
  - Memory Map and Register Definitions
    285
  - Register Descriptions
    287
- Interrupts
  307
  - Functional Description
    308
  - Introduction
    313
  - Register Descriptions
    315
  - Programming Model
    327
- Soft Reset
  328
  - Reset
    329
  - Introduction
    335
  - Features
    336
- External Signal Descriptions
  337
- Detailed Signal Descriptions
  338
- Memory Map and Register Definition
  341
- Register Descriptions
  343
- Functional Description
  373
- Basic Architecture
  374
- General-Purpose Chip-Select Machine (GPCM)
  376
- SDRAM Machine
  390
- User-Programmable Machines (Upms)
  400
  - Upm Requests
    401
  - Programming the Upms
    403
  - Upm Signal Timing
    405
- Application Information
  421
- Bus Turnaround
  424
- Interfacing to SDRAM
  425

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Freescale Semiconductor Symphony DSP56724 Manuals

Freescale Semiconductor Symphony DSP56724 Reference Manual (436 pages)

Table of Contents

Symphony DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual

Chapter 1 Introduction

Chapter 2 Signal Descriptions

Chapter 3 Memory Map 3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

Chapter 9 Enhanced Serial Audio Interface (ESAI, ESAI_1, ESAI_2, ESAI_3)

Chapter 10 Serial Host Interface (SHI, SHI_1) 10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1

Chapter 14 Shared Bus Arbiter 14.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1

Chapter 17 EMC Burst Buffer

Chapter 20 Chip Configuration Module

Chapter 16 Shared Peripheral Bus

Chapter 21 External Memory Controller (EMC)

Chapter 22 JTAG Controller 22.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1

Chapter 15 Shared Memory (Shared Memory)

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