Figure 15.7 Master Receive Mode Operation Timing 1; Figure 15.8 Master Receive Mode Operation Timing 2 - Renesas H8S/2368 Series Hardware Manual

Master transmit mode
SCL
(master output)
SDA
(master output)
SDA
(slave output)
TDRE
TEND
TRS
RDRF
ICDRS
ICDRR
User
processing
[1] Clear TDRE after clearing
TEND and TRS

Figure 15.7 Master Receive Mode Operation Timing 1

SCL
9
(master output)
SDA
A
(master output)
SDA
(slave output)
RDRF
RCVD
ICDRS
Data n-1
ICDRR
Data n-1
User
[5] Read ICDRR and clear RDRF
processing

Figure 15.8 Master Receive Mode Operation Timing 2

Rev. 2.00, 05/03, page 606 of 820
Master receive mode
9 1 2
Bit 7 Bit 6
A
[2] Read ICDRR (dummy read)
1 2 3
Bit 7 Bit 6 Bit 5
after setting RCVD.
3 4 5
Bit 5 Bit 4 Bit 3
4 5 6 7
Bit 4 Bit 3 Bit 2 Bit 1
[7] Read ICDRR, clear RDRF,
and clear RCVD.
6 7 8 9
A
Bit 2 Bit 1 Bit 0
Data 1
[3] Read ICDRR
8 9
A/
Bit 0
Data n
Data n
[6] Issue stop
condition
[8] Set slave
1
Bit 7
Data 1
receive mode