Figure 17.7 Operation Timing In Master Receive Mode (1); Figure 17.8 Operation Timing In Master Receive Mode (2) - Renesas H8S/2437 Hardware Manual

Master transmit mode
SCL
(master output)
SDA
(master output)
SDA
(slave output)
TDRE
TEND
TRS
RDRF
ICDRS
ICDRR
User
processing
[1] Clear TDRE after clearing
TEND and TRS

Figure 17.7 Operation Timing in Master Receive Mode (1)

SCL
9
(master output)
SDA
A
(master output)
SDA
(slave output)
RDRF
RCVD
ICDRS
Data n-1
ICDRR
Data n-1
User
[5] Read ICDRR after setting RCVD
processing

Figure 17.8 Operation Timing in Master Receive Mode (2)

Master receive mode
9 1 2
Bit 7 Bit 6
A
[2] Read ICDRR (dummy read)
1 2 3 4
Bit 7 Bit 6 Bit 5 Bit 4
3 4 5 6
Bit 5 Bit 4 Bit 3 Bit 2
5 6 7
Bit 3 Bit 2 Bit 1 Bit 0
Data n
[7] Read ICDRR and clear RCVD
Rev. 1.00, 09/03, page 495 of 704
7 8 9
A
Bit 1 Bit 0 Bit 7
Data 1
Data 1
[3] Read ICDRR
8 9
A/
Data n
[6] Issue stop
condition
[8] Set slave
receive mode
1