Sending A Break Signal; Receive Data Sampling Timing And Receive Margin (Asynchronous Mode) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
14.6.5

Sending a Break Signal

The I/O condition and level of the TxD pin are determined by the SPB2IO and SPB2DT bits in the serial port register
(SCSPTR). This feature can be used to send a break signal.
Until TE bit is set to 1 (enabling transmission) after initializing, the TxD pin does not work. During the period, mark
status is performed by the SPB2DT bit. Therefore, the SPB2IO and SPB2DT bits should be set to 1 (high level output).
To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low level), then clear the TE bit
to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current
transmission state, and 0 is output from the TxD pin.
14.6.6

Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)

This module operates on a base clock with a frequency 16 or 8 times the bit rate. In reception, the falling edge of the start
bit is sampled at the base clock to perform synchronization internally. Receive data is latched at the rising edge of the
eighth or fourth base clock pulse. When this module operates on a base clock with a frequency 16 times the bit rate, the
receive data is sampled at the timing shown in Figure 14.19.
0
Base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode
(Operation on a Base Clock with a Frequency 16 Times the Bit Rate)
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
1
M = (0.5 − ) − (L − 0.5) F −
2N
Where: M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16 or 8)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation 1, if F = 0, D = 0.5 and N = 16, the receive margin is 46.875%, as given by equation 2.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
16 clocks
8 clocks
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
–7.5 clocks
Start bit
D − 0.5
(1 + F) × 100 %
N
14. Serial Communication Interface with FIFO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+7.5 clocks
D0
0 1 2 3 4 5
D1
14-49