Figure 17.8 Master Receive Mode Operation Timing Example (1) (Mls = Ackb = 0, Wait = 1) - Renesas H8S/2158 User Manual

13. Clear the WAIT bit in ICMR to 0 to clear wait mode.
Read ICDR receive data and clear the IRIC flag to 0. Clearing of the IRIC flag should be done
while WAIT = 0. (If the WAIT bit is cleared to 0 after clearing the IRIC flag and then an
instruction to issue a stop condition is executed, the stop condition cannot be issued because
the output level of SDA is fixed as low.)
14. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL
is high, and generates the stop condition.
Master tansmit mode
SCL
(master output) 9
SDA A
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing
[1] TRS cleared to 0
WAIT set to 1
ACKB cleared to 0
Figure 17.8 Master Receive Mode Operation Timing Example (1)
Master receive mode
1 2 3 4
Bit 7 Bit 6 Bit 5 Bit 4
Data 1
[2] ICDR read
[2] IRIC clear
(dummy read)
(MLS = ACKB = 0, WAIT = 1)
Section 17 I
5 6 7 8
Bit 3 Bit 2 Bit 1 Bit 0
[3]
[4] IRIC clear
Rev. 3.00 Jan 25, 2006 page 521 of 872
2
C Bus Interface (IIC)
9 1 2 3
Bit 7 Bit 6 Bit 5 Bit 4
Data 2
[5]
A
Data 1
[6] ICDR read [7] IRIC clear
(Data 1)
REJ09B0286-0300
4 5
Bit 3