ST STM32L4+ Series Reference Manual page 1235

RM0432
All sources are ORed before entering the timer BRK or BRK2 inputs, as per
below.
Core Lockup
PVD
RAM parity Error
ECC Error
CSS
BKINP
BKIN inputs
from AF
controller
BKCMP1P
COMP1 output
BKCMP2P
COMP2 output
DFSDM
BREAK output
BK2INP
BKIN2 inputs
from AF
controller
BK2CMP1P
COMP1 output
BK2CMP2P
COMP2 output
DFSDM
BREAK output
Note: An asynchronous (clockless) operation is only guaranteed when the programmable filter is
disabled. If it is enabled, a fail safe clock mode (for example by using the internal PLL and/or
the CSS) must be used to guarantee that break events are handled.
Figure 327. Break and Break2 circuitry overview
Lockup LOCK
PVD LOCK
Parity LOCK
ECC LOCK
BKINE
BKCMP1E
BKCMP2E
BKDFBKxE
BK2INE
BK2CMP1E
BK2CMP2E
BK2DFBKxE
Advanced-control timers (TIM1/TIM8)
System break requests
BKF[3:0] BKP
Filter
Application break requests
BK2F[3:0] BK2P
Filter
Application break requests
RM0432 Rev 6
Figure 327
SBIF flag
Software break requests: BG
BIF flag
BKE
Software break requests: B2G
B2IF flag
BK2E
BRK request
BRK2 request
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