Figure 15.11 Slave Receive Mode Operation Timing (1); Figure 15.12 Slave Receive Mode Operation Timing (2) - Renesas H8 Series Hardware Manual

3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
4. The last byte data is read by reading ICDRR.
SCL
(Master output)
SDA
(Master output)
SCL
(Slave output)
SDA
(Slave output)
RDRF
ICDRS
ICDRR
User
processing

Figure 15.11 Slave Receive Mode Operation Timing (1)

SCL
(Master output)
SDA
(Master output)
SCL
(Slave output)
SDA
(Slave output)
RDRF
ICDRS
ICDRR
User
processing

Figure 15.12 Slave Receive Mode Operation Timing (2)

9 1 2
Bit 7 Bit 6
A
Data 1
[2] Read ICDRR (dummy read)
9 1 2 3
Bit 7 Bit 6 Bit 5
A
Data 1
Section 15 I
3 4 5 6
Bit 5 Bit 4 Bit 3 Bit 2
4 5 6 7
Bit 4 Bit 3 Bit 2 Bit 1
[3] Set ACKBT
Rev. 1.00 Aug. 28, 2006 Page 265 of 400
2
C Bus Interface 2 (IIC2)
7 8 9 1
Bit 1 Bit 0 Bit 7
A
Data 2
Data 1
[2] Read ICDRR
8 9
Bit 0
A
Data 2
Data 1
[3] Read ICDRR [4] Read ICDRR
REJ09B0268-0100