Figure 17.10 Slave Receive Mode Operation Timing Example (1) (Mls = Ackb = 0) - Renesas H8S/2158 User Manual

Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA is
changed from low to high when SCL is high and the stop condition is detected, the BBSY flag in
ICCR is cleared to 0.
Start condition issuance
SCL
(master output)
SCL
(slave output)
SDA
(master output)
SDA
(slave output)
RDRF
IRIC
ICDRS
ICDRR
User processing
Figure 17.10 Slave Receive Mode Operation Timing Example (1)
1 2 3 4
Bit 7 Bit 6 Bit 5 Bit 4
Slave address
(MLS = ACKB = 0)
Section 17 I
5 6 7 8
Bit 3 Bit 2 Bit 1 Bit 0
R/W
[5] ICDR read
Rev. 3.00 Jan 25, 2006 page 523 of 872
2
C Bus Interface (IIC)
9 1 2
Bit 7 Bit 6
Data 1
[4]
A
Interrupt
request
generation
Address + R/W
Address + R/W
[5] IRIC clear
REJ09B0286-0300