Figure 15.11 Slave Receive Mode Operation Timing 1; Figure 15.12 Slave Receive Mode Operation Timing 2 - Renesas H8S/2368 Series Hardware Manual

16-bit single-chip microcomputer
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before clearing RDRF, to be returned to the master device, is reflected to the next transmit
frame.
4. The last byte data is read by reading ICDRR.
SCL
(master output)
SDA
(master output)
SCL
(slave output)
SDA
(slave output)
RDRF
ICDRS
ICDRR
User
processing

Figure 15.11 Slave Receive Mode Operation Timing 1

SCL
(master output)
SDA
(master output)
SCL
(slave output)
SDA
A
(slave output)
RDRF
ICDRS
ICDRR
User
processing

Figure 15.12 Slave Receive Mode Operation Timing 2

Rev. 2.00, 05/03, page 610 of 820
9
1
2
Bit 7
Bit 6
A
Data 1
[2] Read ICDRR (dummy read), and clear RDRF.
9
1
2
3
Bit 7
Bit 6
Bit 5
Data 1
3
4
5
6
Bit 5
Bit 4
Bit 3
Bit 2
4
5
6
7
Bit 4
Bit 3
Bit 2
Bit 1
[3] Set ACKBT
[3] Read ICDRR,
7
8
9
Bit 1
Bit 0
Bit 7
A
[2] Read ICDRR, and clear RDRF.
8
9
Bit 0
A/
Data 2
Data 1
[4] Read ICDRR,
and clear RDRF.
and clear RDRF.
1
Data 2
Data 1

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