Figure 17.11 Operation Timing In Slave Receive Mode (1); Figure 17.12 Operation Timing In Slave Receive Mode (2) - Renesas H8S/2437 Hardware Manual

Renesas 16-bit single-chip microcomputer h8s family / h8s / 2600 series
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4. The last-byte data is read by reading ICDRR.
SCL
(master output)
SDA
(master output)
SCL
(slave output)
SDA
(slave output)
RDRF
ICDRS
ICDRR
User
processing

Figure 17.11 Operation Timing in Slave Receive Mode (1)

SCL
(master output)
SDA
(master output)
SCL
(slave output)
SDA
(slave output)
RDRF
ICDRS
ICDRR
User
processing

Figure 17.12 Operation Timing in Slave Receive Mode (2)

9
1
2
Bit 7
Bit 6
A
Data 1
[2] Read ICDRR (dummy read)
9
1
2
3
Bit 7
Bit 6
Bit 5
A
Data 1
3
4
5
6
Bit 5
Bit 4
Bit 3
Bit 2
4
5
6
7
Bit 4
Bit 3
Bit 2
Bit 1
[3] Set ACKBT
Rev. 1.00, 09/03, page 499 of 704
7
8
9
Bit 1
Bit 0
A
[2] Read ICDRR
8
9
Bit 0
A/
Data 1
[4] Read ICDRR
[3] Read ICDRR
1
Bit 7
Data 2
Data 1
Data 2

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